DS80C320-MCG Datasheet, PDF (74/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

High-Speed Microcontroller User’s Guide
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FIVE CYCLE INSTRUCTION TIMING Figure 5–7
Example: MUL A,B
A4h
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*Shaded areas are held in a weak latch on the port until overdriven.
COMPARISON TO THE 8051
The original 8051 had a 12 clock architecture. A machine cycle needed 12 clocks and most instructions
were either one or two machine cycles. Thus except for the MUL and DIV instructions, the 8051 used
either 12 or 24 clocks for each instruction. Furthermore, each cycle in the 8051 used two memory
fetches. In many cases the second fetch was a dummy, and the extra clock cycles were wasted.
The High-Speed Microcontroller uses 4 clocks per cycle. Since a cycle is now aligned with a memory
fetch when possible, most instructions have the same number of cycles as bytes. This leads to more
“categories” than the original 8051. Where there were primarily one and two cycle instructions before,
there are now one, two, three, and four cycle instructions. Multiply and Divide require five cycles. Note
however, that regardless of the number of cycles, each instruction is at least 1.5 and most are 2 to 3 times
faster than its original counterpart. Table 5-1 shows each instruction, the number of clocks used in the
High-Speed Microcontroller and the number used in the 8051 for comparison. The factor by which the
High-Speed Microcontroller improves on the 8051 is shown as the Speed Advantage. A Speed
Advantage of 3.0 means that the High-Speed Microcontroller performs the same instruction three times
faster that the 8051.
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