DS80C320-MCG Datasheet, PDF (94/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

High-Speed Microcontroller User’s Guide
WDCON.2 WTRF - Watchdog Timer Reset Flag. Hardware will set this bit when the Watchdog Timer
causes a reset. Software can read it, but must clear it manually. A Power-fail Reset will also clear the bit.
This bit assists software in determining the cause of a reset. If EWT=0, the Watchdog Timer will have no
affect on this bit.
WDCON.1 EWT - Enable Watchdog Timer Reset. Setting this bit will turn on the Watchdog Timer
Reset function. The Interrupt will not occur unless the EWDI bit in the EIE register is set. A reset will
occur according to the WD1 and WD0 bits in the CKCON register. Setting this bit to a 0 will disable the
reset but leave the timer running.
WDCON.0 RWT - Reset Watchdog Timer. This bit serves as the strobe for the Watchdog function.
During the time-out period, software must set the RWT bit if the Watchdog is enabled. Failing to set the
RWT will cause a reset when the time-out has elapsed. There is no need to set the RWT bit to a 0
because it is self-clearing.
EIE.4 EWDI - Enable Watchdog Interrupt. Setting this bit in software enables the Watchdog Interrupt.
EXIF.0 BGS - Band-Gap Select. Setting this bit to a 1 will allow the use of the Band-gap voltage
reference while in Stop mode. Since this function uses as much as 50 mA, the band-gap is optional in
Stop mode. Setting this bit to a 0 will turn off the Band-gap while in Stop mode. When BGS=0, no
Power-fail interrupt or Power-fail Reset will be available in Stop mode.
PCON.1 STOP. When this bit is set, the program stops execution, clocks are stopped, and the CPU
enters power-down mode.
PCON.0 IDLE. Program execution halts leaving timers, serial ports, and clocks running.
EXIF.2 RGMD - Ring Oscillator Mode. Hardware will set this status bit to a 1 when the clock source is
the Ring Oscillator. Hardware will set this status bit to a 0 when the crystal is the clock source. Refer to
RGSL below for operation of the Ring Oscillator.
EXIF.1 RGSL - Ring Oscillator Select. When set to a 1 by software, the High-Speed Microcontroller
will use a Ring Oscillator to come out of Stop mode without waiting for crystal start-up. This allows an
instantaneous start-up when coming out of Stop mode. It is useful if software needs to perform a short
task, then return to Stop. It is also useful if software must respond quickly to an external event. After the
crystal has performed 65,536 cycles, hardware will switch to the crystal as its clock source. The RGMD
status bit reports on this changeover. When RGSL is set to a 0, the High-Speed Microcontroller will
delay software execution until after the 65,536 clock crystal startup time. RGSL is only cleared by a
power-on reset and is not altered by other forms of reset.
POWER CONSERVATION
The High-Speed Microcontroller is implemented using full CMOS circuitry for low power operation. It
is fully static so the clock speed can be run down to DC. Like other CMOS, the power consumption is
also a function of operating frequency. Although the High-Speed Microcontroller is designed for
maximum performance, it also provides improved power versus work relationships compared with
standard 8051 devices. These topics are discussed in detail below.
The High-Speed Microcontroller provides two power conservation modes. They are similar, but have
different merits and drawbacks. These modes are Idle and Stop. In the original 8051, the Stop mode is
called Power Down. These modes are invoked in the same manner as the original 8051 series.
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