DS80C320-MCG Datasheet, PDF (107/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

High-Speed Microcontroller User’s Guide
SECTION 9: INTERRUPTS
The High-Speed Microcontroller family utilizes a three-priority interrupt system. The number of
interrupts varies according to the specific device. Each source has an independent priority bit, flag,
interrupt vector, and enable. In addition, interrupts can be globally enabled (or disabled). The system is
compatible with the original 8051 family. All of the original interrupts are available.
Several new sources have been added with new associated control and status bits, and new interrupt
vectors. Note that the interrupt vector table can extend from 0000h to 006Bh, so existing code may
require a relocation of the start address to avoid a conflict with the upper end of the vector table. A
summary of all interrupts appears in Table 9-1 below. Note that the D587C550 microcontroller
incorporates several interrupt vectors whose locations differ from those used by the High-Speed
Microcontroller Family or other 8051 derivatives.
INTERRUPT SUMMARY Table 9-1
INTERRUPT
INTERRUPT NATURAL
FLAG
ENABLE
PRIORITY
VECTOR PRIORITY
CONTROL
Power–fail Indicator
33h
0
PFI (WDCON.4)
EPFI
N/A
(WDCON.5)
External Interrupt 0
03h
1
IE0 (TCON.1)**
EX0 (IE.0)
PX0 (IP.0)
Timer 0 Overflow
0Bh
2
TF0 (TCON.5)*
ET0 (IE.1)
PT0 (IP.1)
External Interrupt 1
13h
3
IE1 (TCON.3)**
EX1 (IE.2)
PX1 (IP.2)
Timer 1 Overflow
1Bh
4
TF1 (TCON.7)*
ET1 (IE.3)
PT1 (IP.3)
Serial Port 0
23h
5
RI_0 (SCON0.0),
ES0 (IE.4)
PS0 (IP.4)
TI_0 (SCON0.1)
Timer 2 Overflow
2Bh
6
TF2 (T2CON.7)
ET2 (IE.5)
PT2 (IP.5)
Serial Port 1
3Bh
7
RI_1 (SCON1.0),
ES1 (IE.6)
PS1 (IP.6)
TI_1 (SCON1.1)
External Interrupt 2
43h
8
IE2 (EXIF.4)
EX2 (EIE.0) PX2 (EIP.0)
External Interrupt 3
4Bh
9
IE3 (EXIF.5)
EX3 (EIE.1) PX3 (EIP.1)
External Interrupt 4
53h
10
IE4 (EXIF.6)
EX4 (EIE.2) PX4 (EIP.2)
External Interrupt 5
5Bh
11
IE5 (EXIF.7)
EX5 (EIE.3) PX5 (EIP.3)
Watchdog Interrupt
63h
12
WDIF (WDCON.3) EWDI (EIE.4) PWDI (EIP.4)
Real –Time Clock
6Bh
13
RTCIF (RTCC.1)
ERTCI (EIE.5)
PRTCI
(EIP.5)
Unless marked these flags must be cleared manually by software.
* Cleared automatically by hardware when the service routine is vectored to.
** If edge triggered, cleared automatically by hardware when the service routine is vectored to. If level
triggered, flag follows the state of the pin.
INTERRUPT OVERVIEW
An interrupt allows the software to react to unscheduled or asynchronous events. When an interrupt
occurs, the CPU is expected to “service” the interrupt. This service takes the form of an Interrupt Service
Routine (ISR). The ISR resides at a predetermined address as shown in Table 9-1. When the interrupt
occurs, the CPU will vector to the appropriate location. It will run the code found at this location, staying
in an interrupt service state until done with the ISR. Once an ISR has begun, it can be interrupted only by
a higher priority interrupt. The ISR is terminated by a return from interrupt instruction (RETI). When an
RETI is performed, the processor will return to the instruction that would have been next when the
interrupt occurred.
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