DS80C320-MCG Datasheet, PDF (110/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

High-Speed Microcontroller User’s Guide
Power-fail Interrupt
Some devices have the ability to generate an interrupt when V_CC drops below a predetermined level.
These devices compare V_CC against an internal reference. If V_CC drops below the level V_PFW , an
interrupt will result (if enabled). Note that the Power-fail Interrupt has the highest priority. The priority
level cannot be altered by the user, but the interrupt can be disabled if not needed. The level of V_PFW is
provided in the data sheet specifications associated with each product. Note that the EPFI bit enables the
Power-fail Interrupt. This bit is not subject to the global interrupt enable (EA). The Power-fail interrupt
is a level-sensitive interrupt and will remain set as long as V_CC remains below V_PFW.
Simulated Interrupts
Software can simulate any interrupt source by setting the corresponding flag bit. This forces an interrupt
condition which will be acknowledged if enabled and is otherwise indistinguishable from the real thing.
Thus an interrupt flag bit should never be set to a logic 1 by software inadvertently. Once an interrupt has
been acknowledged, software cannot prevent or end the interrupt by clearing its flag. However, if for
some reason the interrupt acknowledge is delayed, software may clear the flag and thereby prevent the
interrupt from occurring. One exception is the real-time clock interrupt flag, RTCIF, which cannot be set
in software.
INTERRUPT PRIORITIES
The High-Speed Microcontroller has three interrupt priority levels. These are highest, high, and low.
The Power-fail Interrupt is the only source that has highest priority and this level is fixed. The remaining
sources are individually programmable to either high or low. Low priority is the default. A low priority
interrupt can be interrupted by a high (or highest) priority interrupt. A high priority interrupt can only be
interrupted by the Power-fail interrupt.
When an interrupt occurs and is serviced, its priority determines if its ISR can be interrupted. No
interrupt source of equal or lesser priority can interrupt another source. That is, an incoming interrupt
must be of a higher priority than the one currently being serviced to have priority.
If two interrupt sources of equal priority levels are requested simultaneously, the natural priority is used
to arbitrate. The natural priority is given in Table 9-1. Note that natural priority is only used to resolve
simultaneous requests. Once an interrupt of a given priority is invoked, only a source that is programmed
with a higher priority can intercede.
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