DS80C320-MCG Datasheet, PDF (71/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

TWO CYCLE INSTRUCTION TIMING Figure 5-4
Example: ANL A, direct:
55h addr7-0
High-Speed Microcontroller User’s Guide
INSTRUCTION
FETCH
OPERAND
FETCH
C1
C2
C3
C4
C1
C2
C3
C4
CLK
ALE
PSEN
AD0-
POR
A7-0
PIC
RETURN
DATA
ADDRESS
A15-A8
A7-0
PC+1
RETURN DATA OPER
AND ADDRESS 7-0
ADDRESS
A15-A8
*Shaded areas are held in a weak latch on the port until overdriven.
THREE CYCLE INSTRUCTIONS
Three cycle instructions come in two varieties. The first requires three memory accesses. These are
similar to one and two cycle instructions in that the number of bytes equals the number of cycles.
The second variety is a three cycle instruction that simply requires 12 clocks to perform the function.
This may have one or two bytes. Examples of both types are shown below.
ANL direct, #data
53h
a ₇–a ₀
d7–d0
(3 bytes)
SJMP rel
80h
a ₇–a ₀
(2 bytes)
INC DPTR
A3h
(1 byte)
In the first example, the first memory fetch is the opcode. The second is the location of the destination
register. The third memory fetch is the operand that is used by the instruction. This instruction has three
memory accesses, so it requires three machine cycles. The second example has the operand in the first
byte and the jump location in the second. It requires three cycles to actually perform the jump. The third
example contains simply the opcode, which is one byte. This instruction involves the manipulation of a
16-bit register so it takes longer than 8-bit operations. Figure 5-5 shows the timing of all three types of
three cycle instructions.
71 of 175