DS80C320-MCG Datasheet, PDF (80/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

High-Speed Microcontroller User’s Guide
SECTION 6: MEMORY ACCESS
The High-Speed Microcontroller follows the memory interface convention established for the industry
standard 80C51/80C31. Products in the family may vary, so refer to the specific product data sheet for
any potential differences. Like the 8051 series, the High-Speed Microcontroller uses two memory
segments. These are program memory and data memory. Program memory is read–only and is usually
implemented in ROM or EPROM. Data memory is read/write and is commonly implemented in SRAM.
Memory areas can be implemented as either on-chip, off-chip, or a combination. When using devices
without internal program memory, or if the maximum address of on-chip program or data memory is
exceeded, the device will perform an external memory access using the Expanded memory bus on ports 0
and 2. While serving as a memory bus, port 0 and port 2 do not function as I/O ports, following the
standard 8051 convention of addressing external memory. The PSEN signal will go active low to serve
as a chip enable or output enable when performing a code fetch from external memory. Products with no
on-chip program memory such as the DS80C320 will always use the Expanded bus. These devices have
no Port 0 latch since the port is dedicated for memory operations. Devices which incorporate on-chip
MOVX data memory operate in a similar fashion, except that the RD and WR signals serve as chip
enables when accessing an external SRAM.
Program execution begins at the reset vector, address 0000h. Any reset will cause the next program fetch
to begin at this location. Subsequent branches and interrupts determine how the memory fetch deviates
from sequential addressing. Since all programs begin at 0000h, this will be the beginning address of all
program execution. If on-chip program memory is present, program execution will begin at internal
location 0000h, otherwise external program memory will be used.
INTERNAL PROGRAM MEMORY
Some members of the High-Speed Microcontroller family incorporate internal EPROM or ROM for
program storage. On-chip program memory begins at address 0000h and is contiguous through the
amount of on-chip memory. Exceeding the maximum address of on–chip memory will cause the device
to perform an external memory access using the Expanded memory bus on ports 0 and 2. For example, if
the on-chip program memory is 16KB, then it lies between 0000h and 3FFFh in a contiguous area. Thus
a fetch at program memory location 4000h would be directed to the Expanded bus. Restricting memory
operations within the on-chip memory allows ports 0 and 2 to be used for general purpose I/O. For more
information concerning memory size for a specific device, consult the specific data sheet.
The High-Speed Microcontroller family was designed to be compatible with industry standard 87C51FB
programming tools. A number of third-party device programmers are available which support Dallas
Semiconductor products. In addition, Dallas Semiconductor manufactures the DS87000 Microcontroller
Programmer, specifically designed for EPROM-based members of the High-Speed Microcontroller
family.
INTERNAL DATA MEMORY
Some members of the High-Speed Microcontroller family incorporate internal SRAM for additional data
storage. This memory is addressed via MOVX commands, and is in addition to the 256 bytes of
scratchpad memory. On-chip data memory begins at address 0000h and is contiguous through the
amount of on-chip memory. Exceeding the maximum address of on-chip memory will cause the device
to perform an external memory access using the Expanded memory bus on ports 0 and 2. For example, if
the on-chip program memory is 1KB, then it lies between 0000h and 03FFh in a contiguous area. Thus a
MOVX instruction affecting memory location 0400h would be directed to the Expanded bus.
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