DS80C320-MCG Datasheet, PDF (109/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

High-Speed Microcontroller User’s Guide
If the Power Management Modes are utilized, the designer must remember that edge triggered interrupts
must be high and low for one machine cycle before being recognized. This means that in PMM1 it will
require 128 external clock cycles to recognize a level sensitive interrupt. Similarly, in PMM2 it will
require 2048 external clock cycles to recognize a level sensitive interrupt. As a result, the interrupt
latency for these interrupts will be slightly longer in PMM1or PMM2.
Timer Interrupts
The High-Speed Microcontroller incorporates three 16-bit programmable timers, each of which can
generate an interrupt. In addition, some members of the family incorporate a programmable watchdog
timer. The three programmable timers operate in the same manner as the 80C52. Each timer has an
independent interrupt enable, flag, vector, and priority. The Watchdog Timer also has its own interrupt
enable, flag, and priority.
Timers 0, 1, and 2 will set their respective flags when the timer overflows from a full condition,
depending on its mode. This flag will be set regardless of the interrupt enable state. If the interrupt is
enabled, this event will also cause a jump to the corresponding interrupt vector. For timers 0 and 1, the
flags are cleared when the processor jumps to the interrupt vector. Thus these flags are not available for
use by the interrupt service routine (ISR), but are available outside of the ISR and in applications that
don’t acknowledge the interrupt (i.e., jump to the vector). If the interrupt is not acknowledged, then
software must manually clear the flag bit. In timer 2, jumping to the interrupt vector does not clear the
flag, so software must always clear it manually. Timer 0 and 1 flag bits reside in the TCON register.
Timer 2 flag bit resides in the T2CON register. The interrupt enables and priorities for timers 0, 1, and 2
reside in the IE and IP registers respectively.
The Watchdog Interrupt usually has a different connotation than the Timer interrupts. Unless the
Watchdog is being used as a very long timer, the interrupt means the software has failed to reset the
counter and may be lost. The ISR can attempt to determine the system state. If the Watchdog is not
cleared, the CPU will be reset in 512 clocks if EWT=1. Like other sources, the Watchdog Timer has a
flag bit, an enable, and a priority. It also has its own vector. These are summarized in table 9-1.
Serial Communication Interrupts
Each UART is capable of generating an interrupt. The UART has its own interrupt enable, vector, and
priority. The UART differs from other sources as it has two flags. These are used by the ISR to
determine whether the interrupt comes from a received word or a transmitted one. Unlike the timers, the
UART flags are not altered when the interrupt is serviced. Software must change them manually.
When a UART finishes the transmission of a word, an interrupt will be generated (if enabled). Likewise,
the UART will generate an interrupt when a word is completely received. The CPU will not be notified
until the word is completely received or transmitted.
Real-Time Clock
The DS87C530 real-time clock (RTC) has the ability to assert an RTC interrupt if enabled. The alarm
can be programmed for a specific time once per day, or can be a recurring alarm once per hour, minute,
second, or subsecond. This interrupt has the lowest priority of all interrupts, but can be used to bring the
device out of Stop mode if desired. More information on this interrupt can be found in Section 14.
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