DS80C320-MCG Datasheet, PDF (53/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

B Register (B)
7
SFR F0h B.7
RW-0
6
B.6
RW-0
5
B.5
RW-0
4
B.4
RW-0
High-Speed Microcontroller User’s Guide
3
B.3
RW-0
2
B.2
RW-0
1
B.1
RW-0
0
B.0
RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
B.7-0
Bits 7-0
B Register. This register serves as a second accumulator for certain arithmetic
operations. It is functionally identical to the B register found in the 80C32.
Real Time Alarm Subsecond Register (RTASS)
7
6
5
4
3
SFR F2h RTASS.7 RTASS.6 RTASS.5 RTASS.4 RTASS.3
RW-* RW-* RW-* RW-* RW-*
2
RTASS.2
RW-*
1
RTASS.1
RW-*
0
RTASS.0
RW-*
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset, * = See description
RTASS.7-0
Bits 7-0
Real Time Alarm Subsecond. These bits represent the subsecond alarm which
will be compared against the RTC Subsecond register (RTCSS;FAh). The
ability of a match between the two registers to cause an alarm is controlled by
the RTC Subsecond Register Compare Enable bit (RTCC.7). The contents of
this register will be indeterminate following a no-battery reset, and unchanged
by all other forms of reset.
Real Time Alarm Second Register (RTAS)
7
6
5
4
SFR F3h
0
0
RTAS.5 RTAS.4
RW-0 RW-0 RW-* RW-*
3
RTAS.3
RW-*
2
RTAS.2
RW-*
1
RTAS.1
RW-*
0
RTAS.0
RW-*
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset, * = See description
Bits 7-6
RTAS.5-0
Bits 5-0
Reserved. These bits will be 0 when read.
Real Time Alarm Second. These bits represent the second alarm which will be
compared against the RTC Second register (RTCS;FBh). The ability of a match
between the two registers to cause an alarm is controlled by the RTC Second
Register Compare Enable bit (RTCC.6). This register should only be loaded
with values from 0 to 3Bh (0 to 59 seconds). The contents of this register will be
indeterminate following a no-battery reset (except bits 7, 6), and unchanged by
all other forms of reset.
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