DS80C320-MCG Datasheet, PDF (151/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

High-Speed Microcontroller User’s Guide
Reception begins when a falling edge is detected as part of the incoming start bit on the RXD pin. The
RXD pin is then sampled according to the baud rate speed. The 9^th bit is placed in the RB8 bit location in
SCON (SCON0.2 or SCON1.2). When a stop bit has been received, the data value will be transferred to
the SBUF receive register (hex address 99 or C1). The RI bit (SCON0.0 or SCON1.0) will be set to
indicate that a byte has been received. At this time, the UART can receive another byte.
Once the baud rate generator is active, reception can begin at any time. The REN bit (SCON0.4 or
SCON1.4) must be set to a logic 1 to allow reception. The falling edge of a start bit on the RXD pin will
begin the reception process. Data must be shifted in at the selected baud rate. At the middle of the 9th bit
time, certain conditions must be met to load SBUF with the received data.
1. RI must = 0, and either
2. If SM2 = 0, the state of the 9th bit doesn’t matter, or
3. If SM2 = 1, the state of the 9th bit must = 1.
If these conditions are true, then SBUF will be loaded with the received byte, RB8 will be loaded with the
9^th bit, and RI will be set. If these conditions are false, then the received data will be lost (SBUF and RB8
not loaded) and RI will not be set. Regardless of the receive word status, after the middle of the stop bit
time, the receiver will go back to looking for a 1 to 0 transition on RXD.
Data is sampled in a similar fashion to Mode 1 with the majority voting on three consecutive samples.
Mode 2 uses the sample divide by 16 counter with either the oscillator divided by 2 or 4.
Mode 3
This mode has the same operation as Mode 2, except for the baud rate source. As shown in Figure 12-4,
Mode 3 can use Timer 1 or 2 for Serial Port 0 and Timer 1 for Serial Port 1. The bit shifting and protocol
are the same.
FRAMING ERROR DETECTION
A framing error occurs when a valid stop bit is not detected. This results in the possible improper
reception of the serial word. The UART can detect a framing error and notify the software. Typical
causes of framing errors are noise and contention. The Framing Error condition is reported in the SCON
register for the corresponding UART.
The Framing Error bit, FE, is located in SCON0.7 or SCON1.7. Note that this bit normally serves as
SM0 and is described as SM0/FE_0 or SM0/FE_1 in the register description. Framing Error information
is made accessible by the Framing Error Detection Enable bit. It is SMOD0 located at PCON.6. When
SMOD0 is set to a logic 1, the framing error information is shown in SM0/FE (SCON0.7 or SCON1.7).
When SMOD0 is set to a logic 0, the SM0 function is accessible. The information for bits SM0 and FE is
actually stored in different registers. Changing SMOD0 only changes which register is accessed; not the
contents of either.
The FE bit will be set to a 1 when a framing error occurs. It must be cleared by software. Note that the
SMOD0 state must be 1 while reading or writing the FE bit. Also note that receiving a properly framed
serial word will not clear the FE bit. This must be done in software.
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