DS80C320-MCG Datasheet, PDF (57/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

RTCRE
Bit 3
RTCWE
Bit 2
RTCIF
Bit 1
RTCE
Bit 0
High-Speed Microcontroller User’s Guide
RTC Read Enable. This bit temporarily halts internal updating of the RTC to
allow software to read the current time. No loss of time will occur. This bit will
be cleared to 0 following any reset. Attempts to set the RTCRE and RTCWE
bits simultaneously will be ignored. When this bit is cleared, software must wait
4 machine cycles before setting either the RTCRE or RTCWE bit again.
0 = Reads of the RTC clock registers (RTCSS;FAh, RTCS;FBh, RTCM;FCh,
RTCH;FDh, RTCD0;FEh, RTCD1;FFh) are prohibited and will return erroneous
values.
1 = Reads of the RTC clock registers are permitted during a 1 ms window
starting from the time the bit is set. Immediately after setting this bit, software
must wait 4 machine cycles to allow all time registers to synchronize. This bit
should be cleared by the user when the desired reads are complete, although it
will clear automatically within 1.95 ms if not cleared in software.
RTC Write Enable. This bit temporarily halts the RTC to allow software to
update the current time. No loss of time will occur. This bit can only be
modified using a Timed Access procedure. Changing this bit from 1 to 0 will
reset the RTCSS register to 00h.This bit will be cleared to 0 following any reset.
0 = Writes to the RTC clock registers (RTCSS;FAh, RTCS;FBh, RTCM;FCh,
RTCH;FDh, RTCD0;FEh, RTCD1;FFh) are ignored. Attempts to set the
RTCRE and RTCWE bits simultaneously will be ignored. When this bit is
cleared, software must wait 4 machine cycles before setting either the RTCRE
or RTCWE bit again.
1 = Writes to the RTC clock registers are permitted during a 1 ms window
starting from the time this bit is set. Immediately after setting this bit, software
must wait 4 machine cycles to allow all time registers to synchronize. This bit
should be cleared by the user when the desired updates are complete, although it
will clear automatically after 1.95 ms if not cleared in software.
RTC Interrupt Flag. This bit indicates that a RTC alarm match has been made
between all the enabled alarm registers and their corresponding clock registers.
This bit will generate an RTC Interrupt if the ERTCI bit (EIE.5) is set, and must
be cleared by software following an interrupt. RTC interrupts cannot be
generated by setting this bit. Clearing all alarm compare enable bits (RTCC.7-4)
will also clear this bit. This bit will be indeterminate following a no–battery
reset, and is unaffected by all other resets. This bit cannot be set in software.
0 = No RTC interrupts are pending.
1 = RTC Interrupt is pending/active.
RTC Enable. This bit enables/disables the RTC oscillator, halting the RTC.
This bit must be accessed using a Timed Access procedure. This bit will be
indeterminate following a no-battery reset, and is unaffected by all other resets.
If RTC operation is desired, it must be enabled following battery application.
0 = RTC oscillator is disabled.
1 = RTC oscillator is enabled.
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