DS80C320-MCG Datasheet, PDF (95/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

High-Speed Microcontroller User’s Guide
IDLE MODE
Idle mode suspends all CPU processing by holding the program counter in a static state. No program
values are fetched and no processing occurs. This saves considerable power versus full operation. The
virtue of Idle mode is that it uses half the power of the operating state, yet reacts instantly to any interrupt
conditions. All clocks remain active so the timers, Watchdog, Serial Port, and Power Monitor functions
are all working. Since all clocks are running, the CPU can exit the Idle state using any of the interrupt
sources.
Software can invoke the Idle mode by setting the IDLE bit in the PCON register at location 87h. The bit
is located at PCON.0. The instruction that executes this step will be the last instruction prior to freezing
the program counter. Once in Idle, all resources are preserved. There are two ways to exit the Idle mode.
First, any interrupt (that is enabled) will cause an exit. This will result in a jump to the appropriate
interrupt vector. The IDLE bit in the PCON register will be cleared automatically. On returning from
this vector using the RETI instruction, the next address will be the one immediately after the instruction
that invoked the Idle state.
The Idle mode can also be removed using a reset. Any of the three reset sources can do this. On
receiving the reset stimulus, the CPU will be placed in a reset state and the Idle condition cleared. When
the reset stimulus is removed, software will begin execution as for any reset. Since all clocks are active,
there will be no delay after the reset stimulus is removed. Note that if enabled, the Watchdog Timer
continues to run during Idle and must be supported.
STOP MODE
Stop mode is the lowest power state that the High-Speed Microcontroller can enter. This is achieved by
stopping all on-chip clocks, resulting in a fully static condition. No processing is possible, timers are
stopped, and no serial communication is possible. Processor operation will halt on the instruction that
sets the STOP bit. The internal amplifier that excites the external crystal will be disabled, halting crystal
oscillation in Stop mode. Table 7-1 shows the state of the processor pins in Idle and Stop modes.
Stop mode can be exited in two ways. First, like the 8052 microcontrollers, a non-clocked interrupt such
as the external interrupts or the power-fail interrupt can be used. Clocked interrupts such as the watchdog
timer, internal timers, and serial ports will not operate in Stop mode. Note that the band-gap reference
must be enabled in order to use the power-fail interrupt to exit Stop mode, which will increase Stop mode
current. Processor operation will resume with the fetching of the interrupt vector associated with the
interrupt that caused the exit from Stop mode. When the interrupt service routine is complete, an RETI
will return the program to the instruction immediately following the one that invoked the Stop mode.
A second method of exiting Stop mode is with a reset. The watchdog timer reset is not available as a
reset source because no timers are running in Stop mode. An external reset via the RST pin will
unconditionally exit the device from Stop mode. If the BGS bit is set, the device will provide a reset
while in Stop mode if V_CC should drop below the V_RST level. If the BGS bit is 0, then a dip in power
below V_RST will not cause a reset. For example, if V_CC should drop to a level of V_RST -0.5V, then return
to the full level, no reset will be generated. For this reason, use of the band–gap reference is
recommended if a brownout condition is possible in Stop mode. If power fails completely (V_CC =0V),
then a power on reset will still be performed when V_CC is reapplied regardless of the state of the BGS bit.
Processor operation will resume execution from address 0000h like anyother reset.
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