DS80C320-MCG Datasheet, PDF (104/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

High-Speed Microcontroller User’s Guide
SECTION 8: RESET CONDITIONS
The High-Speed Microcontroller provides several ways to place the CPU in a reset state. It also offers
the means for software to determine the cause of a reset. The reset state of most processor bits is not
dependent on the type of reset, but selected bits do depend on the reset source. The reset sources and the
reset state are described below.
RESET SOURCES
The High-Speed Microcontroller has three ways of entering a reset state. Each reset source is described
below. They are:
Power-on/Power Fail Reset
Watchdog Timer Reset
External Reset
Power-on/Fail Reset
Members of the High-Speed Microcontroller family incorporate an internal voltage reference which holds
the CPU in the power-on reset state while V_CC is out of tolerance. Once V_CC has risen above the
threshold, the microcontroller will restart the oscillation of the external crystal and count 65536 clock
cycles. The processor will then begin software execution at location 0000h.
The voltage at which the reset state is entered depends on the specific device. If the device does not
contain a precision voltage reference, the power-on reset threshold may be anywhere between 0.8V and
V_CCMIN . If the device incorporates a precision voltage reference, the threshold will be as specified by the
V_RST parameter in the data sheet. This helps the system maintain reliable operation by only permitting
processor operation when voltage is in a know good state.
The processor will exit the reset condition automatically once the above conditions are met. This happens
automatically, needing no external components or action. Execution begins at the standard reset vector
address of 0000h. Software can determine that a Power-on Reset has occurred using the Power-on Reset
flag (POR). It is located at WDCON.6. Since all resets cause a vector to location 0000h, the POR flag
allows software to acknowledge that power failure was the reason for a reset.
Software should clear the POR bit after reading it. When a reset occurs, software will be able to
determine if a power cycle was the cause. In this way, processing may take a different course for each of
the three resets if applicable. When power fails (drops below V_RST ), the power monitor will invoke the
reset state again. This reset condition will remain while power is below the threshold. When power
returns above the reset threshold, a full power-on reset will be performed. Thus a brownout that causes
V_CC to drop below V_RST appears the same as a power up.
Watchdog Timer Reset
The Watchdog Timer is a free running timer with a programmable interval. Software can clear the timer
at anytime, causing the interval to begin again. The Watchdog supervises CPU operation by requiring
software to clear it before the time-out expires. If the timer is enabled and software fails to clear it before
this interval expires, the CPU is placed into a reset state. The reset state will be maintained for two
machine cycles. Once the reset is removed, the software will resume execution at 0000h.
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