DS80C320-MCG Datasheet, PDF (111/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

High-Speed Microcontroller User’s Guide
INTERRUPT ACKNOWLEDGE CYCLE
The process of acknowledging an interrupt requires multiple machine cycles that begin with the setting of
the associated flag. For edge triggered external interrupts and internal interrupt sources, the interrupt
flags are set automatically by hardware. For level sensitive external interrupts, the flags are actually
under control of the external signal, and the flag will rise and fall with the pin level. Each interrupt flag is
sampled once per machine cycle. Later in the same machine cycle, the samples are polled by hardware.
If the sample indicates a pending interrupt and the interrupt is enabled, then on the next machine cycle it
will be acknowledged by the hardware forcing an LCALL to the appropriate vector address. This
LCALL will occur unless blocked by one of the following conditions.
1. An interrupt of equal or greater priority has already been invoked and the RETI instruction has not
been issued to terminate it.
2. The current machine cycle is not the final cycle in the execution of the current instruction.
3. The instruction in progress is an RETI or a write to IP, IE, EIP, or EIE.
The individual interrupt sources and associated enable and priority bits are shown in Figure 9-1. While
the final selection of the appropriate interrupt vector address is referred to as a polling process, this
function is actually performed in a single machine cycle using combinatorial logic.
INTERRUPT LATENCY
Interrupt response will require a varying amount of time depending on the state of the microcontroller
when the interrupt occurs. If the microcontroller is performing an ISR with equal or greater priority, the
new interrupt will not be invoked. In other cases, the response time depends on the current instruction.
The fastest possible response to an interrupt is 5 machine cycles. This includes one cycle for detecting
the interrupt and four cycles to perform the LCALL that is inherent in the interrupt request. The
maximum response time (if no other interrupt is in service) occurs if the microcontroller is performing an
RETI instruction, and then executes a MUL or DIV as the next instruction. From the time an interrupt
source is activated (not detected), the longest reaction time is 13 machine cycles. This includes 1 cycle to
detect the interrupt, 3 cycles to finish the RETI, 5 to perform the MUL or DIV, then 4 for the LCALL to
the ISR.
The maximum latency of 13 machine cycle is 52 clocks (13*4). Note that the maximum interrupt latency
of an 8051 is 96 clocks (8 machine cycles @ 12 clocks per machine cycle). The maximum latency for the
High-Speed Microcontroller at 25 MHz is about 2 µs. The use of Power Management modes can further
increase the interrupt latency.
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