DS80C320-MCG Datasheet, PDF (100/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

High-Speed Microcontroller User’s Guide
EFFECT OF CLOCK MODES ON TIMER OPERATION Table 7-4
CD1 CD0
OSC.
CYCLES PER
MACHINE
CYCLE
OSC. CYCLES
PER TIMER
0/1/2 CLOCK
OSC. CYCLES
PER TIMER 2
CLOCK,BAUD
RATE GEN.
OSC. CYCLES
PER SERIAL
PORT CLOCK
MODE 0
OSC. CYCLES PER
SERIAL
PORT CLOCK
MODE 2
TxM=1 TxM=0 T2M=1 T2M=0 SM2=0 SM2=1 SMOD=0 SMOD=1
00
Reserved
01
4
12
4
2
2
12
4
64
32
00
64 (PMM1)
192
64
32
32
3072
64
1024
512
1 1 1024 (PMM2) 3072 1024
512
512
1024
1024 16,348
8192
SWITCHBACK
The switchback feature solves one of the most vexing dilemmas faced by power-conscious systems.
Many applications are unable to use the Stop and Idle modes because they require constant computation.
Traditionally, system designers could not reduce the operating speed below that required to process the
fastest event. This meant that system architects would be forced to operate their systems at the highest
rate of speed even when it was not required. The switchback feature allows a system to operate at a
relatively slow speed, and burst to a faster mode when required by an external event. When this feature is
enabled by setting the Switchback Enable bit, SWB, (PMR.5), a qualified interrupt or serial port reception
or transmission will cause the device to return to divide by 4 mode. A qualified interrupt is defined as an
interrupt which has occurred and been acknowledged. This means that an interrupt must be enabled and
also not blocked by a higher priority interrupt. After the event is complete, software can manually return
the device to the appropriate PMM. The following sources can trigger a switchback:
external interrupt 0/1/2/3/4/5,
serial start bit detected, Serial Port 0/1,
transmit buffer loaded, Serial Port 0/1,
watchdog timer reset,
power–on reset,
external reset.
In the case of a serial port-initiated switchback, the switchback is not generated by the associated
interrupt. This is because a device operating in PMM will not be able to correctly receive a byte of data
to generate an interrupt. Instead, a switchback is generated by a serial port reception on the falling edge
associated with the start bit, if the associated receiver enable bit (SCON0.4 or SCON1.4) is set. For serial
port transmissions, a switchback is generated when the serial port buffer (SBUF0;99h or SBUF1;C1h) is
loaded. This ensures the device will be operating in divide by 4 mode when the data is transmitted, and
eliminates the need for a write to the CD1, CD0 bits to exit PMM before transmitting. The switchback
feature is unaffected by the state of the serial port interrupt flags (RI_0, TI_0, RI_1, TI_1).
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