DS80C320-MCG Datasheet, PDF (43/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

ALEOFF
Bit 2
DME1, DME0
Bit 1
High-Speed Microcontroller User’s Guide
ALE Disable. This bit disables the expression of the ALE signal on the device
pin during all on-board program and data memory accesses. External memory
accesses will automatically enable ALE independent of ALEOFF.
0 = ALE expression is enabled.
1 = ALE expression is disabled.
Data Memory Enable 1-0. These bits determine the functional relationship of
the first 1024 bytes of data memory. Three memory configurations are
supported to allow either external data memory access through the expanded
multiplexed address/data bus of Ports 0 and Port 2, internal SRAM data memory
access, or read-only access to EPROM programming information. Note these
bits are cleared after a reset, so access to the internal SRAM is prohibited until
these bits are modified.
DME1
0
0
DME0
0
1
1
0
1
1
DATA MEMORY
ADDRESS RANGE
0000h – FFFFh
0000h – 03FFh
0400h - FFFFh
Reserved
0000h – 03FFh
0400h – FFFBh
FFFCh
FFFDh - FFFFh
MEMORY ACCESS
External Data Memory (default)
Internal SRAM data Memory
External Data Memory
Reserved
Internal SRAM data Memory
Reserved
System Control Byte (EPROM Read Only)
Reserved
The System Control Byte is a special EPROM location that contains nonvolatile
system information. This byte is set during EPROM programming and is not
alterable by software. This register can only be read when both Data Memory
Enable bits are set. The user must be sure that this location is programmed by the
of a special programming utility supplied with the programming device.
System Control Byte Description 9EPROM; FFFCh)
Bits 7-3
Reserved. These bits will read 1. These bits should be set to 1 during EPROM
programming.
LB3, LB2, LB1
Bits 2-0
EPROM Program Lock Bit 301. These bits show the status of the firmware
security of the on-board EPROM. Bit combinations other than shown are illegal.
LB3 LB2 LB1
EPROM PROTECTION MODE
0 0 0 _{Unconditional verification, full external operation. Additional EPROM programming}
allowed without full device erasure.
0 0 1 Verification using encryption, execution of external MOVC instruction on internal
program memory is disabled. All other program execution and data memory access
allowed. Device must be fully erased before EPROM can be programmed again.
0 1 1 Verification disabled, execution of external MOVC instruction on internal program
memory is disabled, and access to internal MOVX data from external program is
prohibited. All other program execution and data memory access allowed. Device must
be fully erased before EPROM can be programmed again.
1 1 1 Verification disabled, external program execution prohibited. Device must be fully
erased before EPROM can be programmed again.
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