DS80C320-MCG Datasheet, PDF (123/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

TCON.6
TCON.5
TCON.4
TCON.3
High-Speed Microcontroller User’s Guide
TR1 - Timer 1 run control. Turns on Timer 1 when this bit is set.
TF0 - Timer 0 overflow flag. Set to one when Timer 0 overflows
from FFh, and cleared when the processor vectors to the interrupt
service routine.
TR0 - Timer 0 run control. Turns on Timer 0 when this bit is set to
a one.
IE1 - Interrupt 1 edge detect. Set by hardware when an edge/level is
detected on INT1 .
TCON.2
TCON.1
IT1 - Interrupt 1 type select. INT1 detects a falling edge when this
bit is set to a 1. INT1 detects a low level when this bit is a 0.
IE0 - Interrupt 0 edge detect. Set by hardware when an edge/level is
detected on INT0 .
TCON.0
IT0 - Interrupt 0 type select. INT0 detects a falling edge when this
bit is set to a 1. INT0 detects a low level when this bit is a 0.
MODE 0
Mode 0 configures either Timer 0 or Timer 1 for operation as a 13-bit Timer/Counter. As shown in
Figure 11-1, bits M1=0 and M0=0 of the TMOD register select this operating mode.
When using Timer 0, TL0 uses only bits 0-4. These bits serve as the 5 LSbs of the 13-bit timer. TH0
provides the 8 MSbs of the 13-bit timer. Bit 4 of TL0 is used as a ripple out to TH0 bit 0, thereby
completely bypassing bits 5 through 7 of TL0. Once the timer is started using the TR0 (TCON.4) timer
enable, the timer will count as long as GATE (TMOD.3) is 0 or GATE is 1 and pin INT0 is 1. It will
count oscillator cycles if C/ T (TMOD.2) is set to a logic 0 and 1 to 0 transitions on T0 (P3.4) if C/ T is
set to a 1. When the 13-bit count reaches 1FFFh (all ones), the next count will cause it to roll over to
0000h. The TF0 (TCON.5) flag will be set and an interrupt will occur if enabled. The upper three bits of
TL0 will be indeterminate.
Note that when used as a timer, the time base may be either oscillator cycles/12 or oscillator cycles/4 as
selected by bits TnM (n=0 or 1) of the CKCON register. This feature is described in more detail below.
Mode 0 operates identically when Timer 1 is used. The same information applies to TL1 and TH1, which
form the 13-bit register. TR1 (TCON.6), INT1 (P3.3), T1 (P3.5), and the relevant C/T (TMOD.6) and
GATE (TMOD.7) bits have the same functions.
MODE 1
Mode 1 configures the timer for 16-bit operation as either a timer or counter. Figure 11-1 shows that bits
M1 = 0 and M0 = 1 of the TMOD register select this operating mode. For Timer n, all of the TLn and
THn registers are used. For example, if Timer 1 is configured in mode 1, then TL1 holds the LSB and
TH1 holds the MSB. Rollover occurs when the timer reaches FFFFh. An interrupt will also occur if
123 of 175