DS80C320-MCG Datasheet, PDF (160/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

High-Speed Microcontroller User’s Guide
Writing an invalid time to these registers (loading the RTCM register with 3Dh or 61 minutes, for
example) will result in an inaccurate count by the RTC. It is the responsibility of the software to ensure
that only valid times are written to these registers.
The procedure for setting an RTC time register is as follows:
1. Disable all interrupts by clearing the EA bit (IE.7),
2. Perform a Timed Access procedure,
3. Set the RTCWE bit (RTCC.2),
4. Wait 4 machine cycles,
5. Write the appropriate register(s) within 1.95 ms of RTCWE being set,
6. Perform a Timed Access procedure,
7. Clear the RTCWE bit (RTCC.2),
8. Enable interrupts by setting the EA bit (IE.7).
USING THE RTC ALARM
The RTC alarm function is used to generate an interrupt when the RTC value matches selected alarm
register values. An alarm can be triggered by a match on one or more of the following alarm registers:
Subsecond (RTASS;F2h), Second (RTAS; F3h), Minute (RTAM; F4h), and Hour (RTAH; F5h). Note
that there is no alarm register associated with the RTC Day Count or Day of Week registers. If an alarm
is desired on a specific date, an alarm can be executed once a day and user software can compare the
current date against the Day Register. It is not necessary to set the RTC Write Enable bit, RTCWE, when
setting the alarm registers.
The alarm can be set to occur on a match with any or all of the alarm registers. An alarm can occur on a
unique time of day, or a recurring alarm can be programmed every subsecond, second, minute, or hour.
Alarms can occur synchronously, when the clock rolls over to match the alarm condition, or
asynchronously, if the alarm registers are set to a value that matches the current time. Note that only one
alarm may occur per subsecond tick. This means that if a synchronous alarm has already occurred during
the current subsecond, software cannot cause an asynchronous alarm in the same subsecond.
The specific alarm registers to be compared are selected by setting or clearing the corresponding compare
enable bits (RTCC.7-4). Any compare bit which is cleared will result in that register being treated as a
Don’t Care when evaluating alarm conditions. Clearing all the compare enable bits will disable the
ability of the RTC to cause an interrupt, and will immediately clear the RTC Interrupt Flag (RTCC.1).
Unlike some interrupts, the RTC flag is not cleared by exiting the RTC interrupt service routine and must
be explicitly cleared in software.
The general procedure for setting the RTC alarm registers to cause a RTC interrupt is as follows:
1. Clear the ERTCI Enable bit (EIE.5),
2. Clear all RTC Alarm Compare enable bits (ANL RTCC, #0Fh),
3. Write one or more RTC Alarm registers,
4. Set the desired RTC Alarm Compare enable bits,
5. Set the ERTCI Enable bit (EIE.5).
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