DS80C320-MCG Datasheet, PDF (98/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

High-Speed Microcontroller User’s Guide
In addition, the DS87C520 and DS87C530 has the capability to operate from the internal ring oscillator
during normal operation, not only during the crystal warm-up period. Table 7-3 summarizes the new
control bits associated with the power management features.
POWER MANAGEMENT AND STATUS BIT SUMMARY Table 7-3
BIT NAME
LOCATION
FUNCTION
RESET READ/WRITE
STATE ACCESS
CD1, CD0 PMR.7–6
Clock Divider Control
0,1
Write: 0,1 anytime;
CD1 CD0 Osc Cycles per Machine Cycle
0
0 Reserved
0
1 4 (Reset Default)
1
0 64 (PMM1)
1
1 1024 (PMM2)
1,0 & 1,1 only when
previously in 0,1
state. Unrestricted
read.
SWB
PMR.5
Switchback Enable
0
0=Interrupts and serial port activity will not affect
Unrestricted
clock divider control bits
1=Enabled Interrupts and serial port activity will
cause a switchback
PIP
STATUS.7
Power Fail Interrupt Status
0
Read Only
0=No power fail interrupt in progress
1=Power fail interrupt in progress
HIP
STATUS.6
High Priority Interrupt Status
0=No high priority interrupt in progress
1=High priority interrupt in progress
0
Read Only
LIP
STATUS.5
Low Priority Interrupt Status
0
Read Only
0=No low priority interrupt in progress
1=Low priority interrupt in progress
SPTA1
STATUS.3
Serial Port 1 Transmitter Activity Status
0
Read Only
0=Serial port 1 transmitter inactive
1=Serial port 1 transmitter active
SPRA1
STATUS.2
Serial Port 1 Receiver Activity Status
0=Serial port 1 receiver inactive
1=Serial port 1 receiver active
0
Read Only
SPTA0
STATUS.1
Serial Port 0 Transmitter Activity Status
0=Serial port 0 transmitter inactive
1=Serial port 0 transmitter active
0
Read Only
SPRA0
STATUS.0
Serial Port 0 Receiver Activity Status
0
Read Only
0=Serial port 0 receiver inactive
1=Serial port 0 receiver active
POWER MANAGEMENT MODE TIMING
The two power management modes reduce power consumption by internally dividing the clock signal to
the device, causing it to operate at a reduced speed. When PMM is invoked, the external crystal will
continue to operate at full speed. The difference is that the device uses 16 (PMM1) or 256 (PMM2)
external clocks to generate each internal clock cycle (C1, C2, C3 or C4) as opposed to 1 clock per internal
clock cycle in divide by 4 mode. This translates to 64 or 1024 external clocks per machine cycle in
PMM1 or PMM2, respectively. Relative timing relationships of all signals when the device is operating
in PMM1 or PMM2 will remain the same as the 4 cycle timing. Note that all internal functions, on-board
timers (including serial port baud rate generation), watchdog timer, and software timing loops will also
run at the reduced speed. Most applications will not find it necessary to attend to this much detail, but the
information is provided for calculating critical timings. Figure 7-2 demonstrates the internal timing
relationships during PMM1.
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