DS80C320-MCG Datasheet, PDF (126/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

TIMER/COUNTER 0 MODE 3 Figure 11-3
High-Speed Microcontroller User’s Guide
OSC INPUT TO TIMER
CLK MODE TIMER INPUT
DIVIDE BY 4 OSC/1
PMM1
OSC/16
PMM2
OSC/256
T0 = P3.4
TR0 = TCON.4
DIVIDE
BY 12
DIVIDE
BY 4
T0M = CKCON.3
0
C/ T = TMOD.2
0 _CLK
0
1
1
TL0 ₇
TF0 = TCON.5
INTERRUPT
GATE = TMOD.3
TF1 = TCON.7 INTERRUPT
INT0 = P3.2
TR1 = TCON.6
0 _{TH0 7}
In Mode 3, Timer 1 stops counting and holds its value. Thus Timer 1 has no practical application while
in Mode 3.
As mentioned above, when Timer 0 is in Mode 3, it uses some of Timer 1’s resources (i.e., TR1 and
TF1). Timer 1 can still be used in Modes 0, 1, and 2 in this situation, but its flexibility becomes
somewhat limited. While it maintains its basic functionality, its inputs and outputs are no longer
available. Therefore when Timer 0 is in Mode 3, Timer 1 can only count oscillator cycles, and it does not
have an interrupt or flag. With these limitations, baud rate generation is its most practical application, but
other time-base functions may be achieved by reading the registers.
TIMER 2
Like Timers 0 and 1, Timer 2 is a full function timer/ counter, however it has several additional
capabilities that make it more useful. Timer 2 has independent control registers in T2CON and T2MOD,
and is based on count registers TL2 and TH2. All of these registers are described in detail below.
T2CON REGISTER SUMMARY
TIMER TWO CONTROL
T2CON.7
T2CON.6
T2CON; C8h
TF2 - Timer 2 Overflow Flag. Hardware will set TF2 when the
Timer 2 overflows from FFFFh or from the count equal to the
capture register in down count mode. It must be cleared to 0 by
software. TF2 will only be set to a 1 if RCLK and TCLK are both
cleared to a 0.
EXF2 - Timer 2 External Flag. Hardware will set EXF2 when a
reload or capture is caused by a falling transition on the T2EX pin
(P1.1). EXEN2 must be set for this function. This flag must be
cleared to 0 by software. Writing a one to this bit will force a timer
interrupt if enabled.
126 of 175