DS80C320-MCG Datasheet, PDF (145/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

High-Speed Microcontroller User’s Guide
the other. Setting either RCLK or TCLK to a logic 1 selects Timer 2 for baud rate generation. RCLK
and TCLK reside in T2CON.4 and TCON.5 respectively.
When using Timer 2 to generate baud rates, the formula will be as follows. Note that the reload value is a
16-bit number as compared with Timer 1, which uses only 8 bits.
o
Mode 1, 3 baud rate =
OscillatorFrequency
32 * (65536 − RCAP2H, RCAP2L)
Note that the 32 in the denominator is a result of the timer being run at a divide by 2, combined with the
divide by 16 applied to timer overflows as mentioned above. Timer 2 normally runs at a divide by either
12 or 4 in auto-reload mode. Setting RCLK or TCLK causes the divide by 2 operation.
This formula provides the derived baud rate for a given RCAP2H, RCAP2L and crystal. Most users
already know what baud rate is desired and want the timer reload value. Thus the equation solves as
follows.
RCAP2H, RCAP2L = 65536 – ^{OscillatorFrequency}
32 * BaudRate
The Timer 2 interrupt is automatically disabled when either RCLK or TCLK is set. Also, the TF2
(TCON.7) flag will not be set on a timer rollover. The manual reload pin, T2EX (P1.1), will not cause a
reload either.
SERIAL I/O DESCRIPTION
A detailed description of each serial mode is given below. A description of framing error detection and
multiprocessor communication follows this section.
Mode 0
This mode is used to communicate in synchronous, half–duplex format with devices that accept the High-
Speed Microcontroller as a master. A functional block diagram and basic timing of this mode are shown
in Figure 12-1. As can be seen, there is one bidirectional data line (RXD) and one shift clock line (TXD)
used for communication. The shift clock is used to shift data into and out of the microcontroller and the
remote device. Mode 0 requires that the microcontroller is the master because the microcontroller
generates the serial shift clocks for both directions. As described above, the shift clock may be selected
to be either divide by 12 or divide by 4 of the oscillator as determined by the SM2 (SCON0.5 or
SCON1.5) bit.
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