DS80C320-MCG Datasheet, PDF (69/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

High-Speed Microcontroller User’s Guide
Due to the limited number of edges within a machine cycle, selected events must occur between edges.
The High-Speed Microcontroller employs sophisticated circuits to create half and quarter clock events.
That is, some events occur between clock edges. Such circuits assure that events occur as precisely as if a
clock edge were available. While being generally transparent to the user, these circuits result in the use of
fractional clocks in the electrical specifications. For example, a time may be specified as 2.5 t_CLCL.
As mentioned above, a machine cycle is the basic timing unit of most functions in the High-Speed
Microcontroller. A machine cycle of the High-Speed Microcontroller is the time required to execute a
single cycle instruction. Almost half the opcodes of the 8051 instruction set are implemented in a single
machine cycle in the High-Speed Microcontroller. The remaining instructions require multiple machine
cycles.
The Power Management Modes implemented on some devices modify the number of clock cycles needed
to execute an instruction. Instead of 4 clocks per machine cycle, power management mode 1 (PMM1)
and power management mode 2 (PMM2) utilize 64 and 1024 clocks per cycle respectively to conserve
power. A full description of the power management modes and their effect on CPU operation is provided
in Section 7.
All instructions are coded within an 8-bit field called an opcode. This single byte must be fetched from
program memory. The opcode is decoded by the CPU. It determines what action the microcontroller will
take and whether more information is needed from memory. If no other memory is needed, then only one
byte was required. Thus the instruction is called a one byte instruction. In some cases, more data is
needed. These will be two or three byte instructions.
In most cases, the number of memory accesses (bytes) needed by an instruction is equal to the number of
machine cycles. Thus single cycle instructions contain one byte, and two cycle instructions have two
bytes. This is true except for the special cases mentioned below.
SINGLE CYCLE INSTRUCTIONS
The standard single cycle instruction timing is shown in Figure 5-3. As mentioned above, there are 126
opcodes that are single cycle instructions. An example of a single cycle instruction is as follows:
DEC
A
14h
TWO CYCLE INSTRUCTIONS
All two cycle instructions require two cycles because they involve two bytes or require two memory
accesses. The first byte is an opcode that instructs the CPU. This is the instruction itself. The second
byte is normally an operand or it specifies the location of the operand. For example, the instruction
“ANL A, direct” uses two cycles and requires two bytes. Two examples are as follows:
ANL A, direct
55h
a7-0
ANL A, #data
54h
d7-d0
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