DS001 Datasheet, PDF (98/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: Pinout Tables
XC2S200 Device Pinouts (Continued)
Additional XC2S200 Package Pins
XC2S200 Pad Name
Bndry
Function Bank PQ208 FG256 FG456 Scan
PQ208
Not Connected Pins
GND
I/O
-
P198 GND* GND*
-
P55
P56
-
-
-
-
0
P199
A5
B7
188
11/02/00
I/O, V_REF
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O, V_REF
V_CCO
GND
I/O
I/O
I/O
I/O
I/O, V_REF
GND
I/O
I/O
I/O
I/O
TCK
V_CCO
V_CCO
0
P200
C6
E8
191
FG256
0
-
-
0
P201
B5
D8
197
C7
200
V_CCINT Pins
C3
C14
D4
D13
E5
E12
-
-
GND* GND*
-
M5
M12
N4
N13
P3
P14
0
-
D6
D7
203
0
-
-
B6
206
V_CCO Bank 0 Pins
E8
F8
-
-
-
-
0
-
-
0
P202
A4
A5
209
D6
212
V_CCO Bank 1 Pins
E9
F9
-
-
-
-
0
P203
B4
C6
215
0
-
V_CCO
V_CCO
-
Bank 0* Bank 0*
-
-
GND* GND*
-
0
P204
E6
B5
218
0
-
D5
E7
221
0
-
-
A4
224
0
-
-
E6
230
0
P205
A3
B4
233
-
-
GND* GND*
-
0
-
C5
A3
236
0
-
-
B3
239
0
-
-
D5
242
0
P206
B3
C5
248
-
P207
C4
C4
-
0
P208
V_CCO
V_CCO
-
Bank 0* Bank 0*
7
P208
V_CCO
V_CCO
-
Bank 7* Bank 7*
V_CCO Bank 2 Pins
H11
H12
-
-
-
-
V_CCO Bank 3 Pins
J11
J12
-
-
-
-
V_CCO Bank 4 Pins
L9
M9
-
-
-
-
V_CCO Bank 5 Pins
L8
M8
-
-
-
-
V_CCO Bank 6 Pins
J5
J6
-
-
-
-
V_CCO Bank 7 Pins
H5
H6
-
-
-
-
GND Pins
A1
A16
B2
B15
F6
F7
F10
F11
G6
G7
G8
G9
G10
G11
H7
H8
H9
H10
J7
J8
J9
J10
K6
K7
K8
K9
K10
K11
L6
L7
04/18/01
L10
L11
R2
R15
T1
T16
Notes:
Not Connected Pins
1. IRDY and TRDY can only be accessed when using Xilinx PCI
P4
R4
-
-
-
-
cores.
2. Pads labelled GND*, V_CCINT*, V_CCO Bank 0*, V_CCO Bank 1*,
V_CCO Bank 2*, V_CCO Bank 3*, V_CCO Bank 4*, V_CCO Bank 5*,
V_CCO Bank 6*, V_CCO Bank 7* are internally bonded to
independent ground or power planes within the package.
3. See "VCCO Banks" for details on V_CCO banking.
DS001-4 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
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