DS001 Datasheet, PDF (56/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: DC and Switching Characteristics
IOB Input Switching Characteristics⁽¹⁾
Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values
shown in "IOB Input Delay Adjustments for Different Standards," page 57.
Speed Grade
-6
-5
Symbol
Description
Device
Min Max Min Max Units
Propagation Delays
T_IOPI
Pad to I output, no delay
All
-
0.8
-
1.0 ns
T_IOPID
Pad to I output, with delay
All
-
1.5
-
1.8 ns
T_IOPLI
Pad to output IQ via transparent latch,
All
-
1.7
-
2.0 ns
no delay
T_IOPLID
Pad to output IQ via transparent latch,
XC2S15
-
3.8
-
4.5 ns
with delay
XC2S30
-
3.8
-
4.5 ns
XC2S50
-
3.8
-
4.5 ns
XC2S100
-
3.8
-
4.5 ns
XC2S150
-
4.0
-
4.7 ns
XC2S200
-
4.0
-
4.7 ns
Sequential Delays
T_IOCKIQ
Clock CLK to output IQ
Setup/Hold Times with Respect to Clock CLK⁽²⁾
All
-
0.7
-
0.8 ns
T_IOPICK / T_IOICKP Pad, no delay
T_IOPICKD / T_IOICKPD Pad, with delay⁽¹⁾
All
1.7 / 0
-
1.9 / 0
- ns
XC2S15 3.8 / 0
-
4.4 / 0
- ns
XC2S30 3.8 / 0
-
4.4 / 0
- ns
XC2S50 3.8 / 0
-
4.4 / 0
- ns
XC2S100 3.8 / 0
-
4.4 / 0
- ns
XC2S150 3.9 / 0
-
4.6 / 0
- ns
XC2S200 3.9 / 0
-
4.6 / 0
- ns
T_IOICECK / T_IOCKICE ICE input
Set/Reset Delays
All 0.9 / 0.01 - 0.9 / 0.01 - ns
T_IOSRCKI
SR input (IFF, synchronous)
All
-
1.1
-
1.2 ns
T_IOSRIQ
SR input to IQ (asynchronous)
All
-
1.5
-
1.7 ns
T_GSRQ
GSR to output IQ
All
-
9.9
-
11.7 ns
Notes:
1. Input timing for LVTTL is measured at 1.4V. For other I/O standards, see the table "Delay Measurement Methodology," page 60.
2. A zero hold time listing indicates no hold time or a negative hold time.
DS001-3 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
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