DS001 Datasheet, PDF (45/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: Functional Description
HSTL Class III
A sample circuit illustrating a valid termination technique for
HSTL_III appears in Figure 45. DC voltage specifications
appear in Table 23 for the HSTL_III standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics.
HSTL Class IV
A sample circuit illustrating a valid termination technique for
HSTL_IV appears in Figure 46.DC voltage specifications
appear in Table 23 for the HSTL_IV standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics
HSTL Class III
V_CCO = 1.5V
V_TT = 1.5V
50Ω
Z = 50
V_REF = 0.9V
DS001_45_061200
Figure 45: Terminated HSTL Class III
Table 23: HSTL Class III Voltage Specification
Parameter
Min
Typ
Max
V_CCO
V_REF ⁽¹⁾
V_TT
V_IH
V_IL
V_OH
V_OL
I_OH at V_OH (mA)
I_OL at V_OL (mA)
1.40
-
-
V_REF + 0.1
-
V_CCO – 0.4
-
–8
24
1.50
0.90
V_CCO
-
-
-
-
-
-
1.60
-
-
-
V_REF – 0.1
-
0.4
-
-
Notes:
1. Per EIA/JESD8-6, "The value of V_REF is to be selected by the
user to provide optimum noise margin in the use conditions
specified by the user."
HSTL Class IV
V_TT = 1.5V
V_CCO = 1.5V
50Ω
V_TT = 1.5V
50Ω
Z = 50
V_REF = 0.9V
DS001_46_061200
Figure 46: Terminated HSTL Class IV
Table 24: HSTL Class IV Voltage Specification
Parameter
Min
Typ
Max
V_CCO
1.40
1.50
1.60
V_REF
-
0.90
-
V_TT
-
V_CCO
-
V_IH
V_REF + 0.1
-
-
V_IL
-
-
V_REF – 0.1
V_OH
V_CCO – 0.4
-
-
V_OL
-
-
0.4
I_OH at V_OH (mA)
–8
-
-
I_OL at V_OL (mA)
48
-
-
Notes:
1. Per EIA/JESD8-6, "The value of V_REF is to be selected by the
user to provide optimum noise margin in the use conditions
specified by the user."
DS001-2 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
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