DS001 Datasheet, PDF (55/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

R
Spartan-II FPGA Family: DC and Switching Characteristics
Global Clock Setup and Hold for LVTTL Standard, with DLL (Pin-to-Pin)
Speed Grade
-6
-5
Symbol
Description
Device
Min
Min
Units
T_PSDLL / T_PHDLL Input setup and hold time relative
All
to global clock input signal for
LVTTL standard, no delay, IFF,⁽¹⁾
with DLL
1.7 / 0
1.9 / 0
ns
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3. DLL output jitter is already included in the timing calculation.
4. A zero hold time listing indicates no hold time or a negative hold time.
5. For data input with different standards, adjust the setup time delay by the values shown in "IOB Input Delay Adjustments for Different
Standards," page 57. For a global clock input with standards other than LVTTL, adjust delays with values from the "I/O Standard
Global Clock Input Adjustments," page 61.
Global Clock Setup and Hold for LVTTL Standard, without DLL (Pin-to-Pin)
Speed Grade
-6
-5
Symbol
Description
Device
Min
Min
Units
T_PSFD / T_PHFD
Input setup and hold time relative
to global clock input signal for
LVTTL standard, no delay, IFF,⁽¹⁾
without DLL
XC2S15
XC2S30
XC2S50
XC2S100
2.2 / 0
2.7 / 0
ns
2.2 / 0
2.7 / 0
ns
2.2 / 0
2.7 / 0
ns
2.3 / 0
2.8 / 0
ns
XC2S150
2.4 / 0
2.9 / 0
ns
XC2S200
2.4 / 0
3.0 / 0
ns
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3. A zero hold time listing indicates no hold time or a negative hold time.
4. For data input with different standards, adjust the setup time delay by the values shown in "IOB Input Delay Adjustments for Different
Standards," page 57. For a global clock input with standards other than LVTTL, adjust delays with values from the "I/O Standard
Global Clock Input Adjustments," page 61.
DS001-3 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 3 of 4
55