DS001 Datasheet, PDF (4/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

R
Spartan-II FPGA Family: Introduction and Ordering Information
Spartan-II Product Availability
Table 2 shows the maximum user I/Os available on the device and the number of user I/Os available for each
device/package combination. The four global clock pins are usable as additional user I/Os when not used as a global clock
pin. These pins are not included in user I/O counts.
Table 2: Spartan-II FPGA User I/O Chart⁽¹⁾
Available User I/O According to Package Type
Device
Maximum
User I/O
VQ100
VQG100
TQ144
TQG144
CS144
CSG144
PQ208
PQG208
FG256
FGG256
XC2S15
86
60
86
(Note 2)
-
-
XC2S30
92
60
92
92
(Note 2)
-
XC2S50
176
-
92
-
140
176
XC2S100
176
-
92
-
140
176
XC2S150
260
-
-
-
140
176
XC2S200
284
-
-
-
140
176
Notes:
1. All user I/O counts do not include the four global clock/user input pins.
2. Discontinued by PDN2004-01.
FG456
FGG456
-
-
-
(Note 2)
260
284
DS001-1 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 1 of 4
4