DS001 Datasheet, PDF (47/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: Functional Description
SSTL2_I
A sample circuit illustrating a valid termination technique for
SSTL2_I appears in Figure 49. DC voltage specifications
appear in Table 27 for the SSTL2_I standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics
SSTL2 Class II
A sample circuit illustrating a valid termination technique for
SSTL2_II appears in Figure 50. DC voltage specifications
appear in Table 28 for the SSTL2_II standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics.
SSTL2 Class I
V_CCO = 2.5V
25Ω
V_TT = 1.25V
Z = 50
50Ω
V_REF = 1.25V
DS001_49_061200
Figure 49: Terminated SSTL2 Class I
Table 27: SSTL2_I Voltage Specifications
Parameter
Min
Typ Max
V_CCO
V_REF = 0.5 × V_CCO
V_TT = V_REF + N⁽¹⁾
V_IH ≥ V_REF + 0.18
V_IL ≤ V_REF – 0.18
V_OH ≥ V_REF + 0.61
V_OL ≤ V_REF – 0.61
I_OH at V_OH (mA)
I_OL at V_OL (mA)
2.3
1.15
1.11
1.33
–0.3⁽³⁾
1.76
-
–7.6
7.6
2.5
1.25
1.25
1.43
1.07
-
-
-
-
2.7
1.35
1.39
3.0⁽²⁾
1.17
-
0.74
-
-
Notes:
1. N must be greater than or equal to –0.04 and less than or
equal to 0.04.
2. V_IH maximum is V_CCO + 0.3.
3. V_IL minimum does not conform to the formula.
SSTL2 Class II
V_TT = 1.25V
V_CCO = 2.5V
50Ω
25Ω
V_TT = 1.25V
50Ω
Z = 50
V_REF = 1.25V
DS001_50_061200
Figure 50: Terminated SSTL2 Class II
Table 28: SSTL2_II Voltage Specifications
Parameter
Min
Typ
Max
V_CCO
V_REF = 0.5 × V_CCO
V_TT = V_REF + N⁽¹⁾
V_IH ≥ V_REF + 0.18
V_IL ≤ V_REF – 0.18
V_OH ≥ V_REF + 0.8
V_OL ≤ V_REF - 0.8
I_OH at V_OH (mA)
I_OL at V_OL (mA)
2.3
2.5
1.15 1.25
1.11 1.25
1.33
–0.3⁽³⁾
1.43
1.07
1.95
-
-
-
–15.2
-
15.2
-
2.7
1.35
1.39
3.0⁽²⁾
1.17
-
0.55
-
-
Notes:
1. N must be greater than or equal to –0.04 and less than or
equal to 0.04.
2. V_IH maximum is V_CCO + 0.3.
3. V_IL minimum does not conform to the formula.
DS001-2 (v2.8) June 13, 2008
Product Specification
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