DS001 Datasheet, PDF (15/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: Functional Description
Figure 9 is a diagram of the Spartan-II family boundary scan
logic. It includes three bits of Data Register per IOB, the
IEEE 1149.1 Test Access Port controller, and the Instruction
Register with decodes.
IOB IOB IOB IOB IOB
IOB.T
DATA IN
1
0
DQ
0
sd
DQ
1
LE
IOB
IOB
IOB
IOB
IOB
IOB
IOB
TDI
Bypass
Register
Instruction Register
IOB
IOB
IOB
IOB
IOB
IOB
IOB
M _TDO
U
X
IOB.I
IOB.Q
IOB.T
1
DQ
0
1
DQ
0
1
DQ
0
sd
D
Q
LE
1
0
sd
DQ
LE
1
0
0
sd
DQ
1
LE
1
DQ
0
sd
DQ
LE
IOB.I
DATAOUT
SHIFT/ CLOCK DATA
CAPTURE REGISTER
UPDATE
Figure 9: Spartan-II Family Boundary Scan Logic
Bit Sequence
The bit sequence within each IOB is: In, Out, 3-State. The
input-only pins contribute only the In bit to the boundary
scan I/O data register, while the output-only pins
contributes all three bits.
From a cavity-up view of the chip (as shown in the FPGA
Editor), starting in the upper right chip corner, the boundary
scan data-register bits are ordered as shown in Figure 10.
BSDL (Boundary Scan Description Language) files for
Spartan-II family devices are available on the Xilinx
website, in the Downloads area.
1
0
EXTEST
DS001_09_032300
DS001-2 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 2 of 4
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