DS001 Datasheet, PDF (42/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: Functional Description
property. This property could have one of the following
seven values.
DRIVE=2
DRIVE=4
DRIVE=6
DRIVE=8
DRIVE=12 (Default)
DRIVE=16
DRIVE=24
Design Considerations
Reference Voltage (V_REF) Pins
Low-voltage I/O standards with a differential amplifier input
buffer require an input reference voltage (V_REF). Provide
the V_REF as an external signal to the device.
The voltage reference signal is "banked" within the device
on a half-edge basis such that for all packages there are
eight independent V_REF banks internally. See Figure 36,
page 39 for a representation of the I/O banks. Within each
bank approximately one of every six I/O pins is
automatically configured as a V_REF input.
Within each V_REF bank, any input buffers that require a
V_REF signal must be of the same type. Output buffers of any
type and input buffers can be placed without requiring a
reference voltage within the same V_REF bank.
Output Drive Source Voltage (V_CCO) Pins
Many of the low voltage I/O standards supported by
Versatile I/Os require a different output drive source voltage
(V_CCO). As a result each device can often have to support
multiple output drive source voltages.
The V_CCO supplies are internally tied together for some
packages. The VQ100 and the PQ208 provide one
combined V_CCO supply. The TQ144 and the CS144
packages provide four independent V_CCO supplies. The
FG256 and the FG456 provide eight independent V_CCO
supplies.
Output buffers within a given V_CCO bank must share the
same output drive source voltage. Input buffers for LVTTL,
LVCMOS2, PCI33_3, and PCI 66_3 use the V_CCO voltage
for Input V_CCO voltage.
Transmission Line Effects
The delay of an electrical signal along a wire is dominated
by the rise and fall times when the signal travels a short
distance. Transmission line delays vary with inductance
and capacitance, but a well-designed board can experience
delays of approximately 180 ps per inch.
Transmission line effects, or reflections, typically start at
1.5" for fast (1.5 ns) rise and fall times. Poor (or
non-existent) termination or changes in the transmission
line impedance cause these reflections and can cause
additional delay in longer traces. As system speeds
continue to increase, the effect of I/O delays can become a
limiting factor and therefore transmission line termination
becomes increasingly more important.
Termination Techniques
A variety of termination techniques reduce the impact of
transmission line effects.
The following lists output termination techniques:
None
Series
Parallel (Shunt)
Series and Parallel (Series-Shunt)
Input termination techniques include the following:
None
Parallel (Shunt)
These termination techniques can be applied in any
combination. A generic example of each combination of
termination methods appears in Figure 41.
Unterminated
Z=50
Double Parallel Terminated
V_TT
V_TT
Unterminated Output Driving
a Parallel Terminated Input
V_TT
Z=50
V_REF
Series Terminated Output Driving
a Parallel Terminated Input
V_TT
Z=50
V_REF
Series Terminated Output
Z=50
V_REF
Z=50
V_REF
Series-Parallel Terminated Output
Driving a Parallel Terminated Input
V_TT
V_TT
Z=50
V_REF
DS001_41_032300
Figure 41: Overview of Standard Input and Output
Termination Methods
Simultaneous Switching Guidelines
Ground bounce can occur with high-speed digital ICs when
multiple outputs change states simultaneously, causing
undesired transient behavior on an output, or in the internal
logic. This problem is also referred to as the Simultaneous
Switching Output (SSO) problem.
Ground bounce is primarily due to current changes in the
combined inductance of ground pins, bond wires, and
DS001-2 (v2.8) June 13, 2008
Product Specification
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