DS001 Datasheet, PDF (66/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: DC and Switching Characteristics
CLB Distributed RAM Switching Characteristics
Symbol
Description
Sequential Delays
T_SHCKO16 Clock CLK to X/Y outputs (WE active, 16 x 1 mode)
T_SHCKO32 Clock CLK to X/Y outputs (WE active, 32 x 1 mode)
Setup/Hold Times with Respect to Clock CLK⁽¹⁾
T_AS / T_AH
T_DS / T_DH
T_WS / T_WH
Clock CLK
F/G address inputs
BX/BY data inputs (DIN)
CE input (WS)
T_WPH
Minimum pulse width, High
T_WPL
Minimum pulse width, Low
T_WC
Minimum clock period to meet address write cycle time
Notes:
1. A zero hold time listing indicates no hold time or a negative hold time.
Speed Grade
-6
-5
Min Max Min Max
-
2.2
-
2.6
-
2.5
-
3.0
0.7 / 0
-
0.7 / 0
-
0.8 / 0
-
0.9 / 0
-
0.9 / 0
-
1.0 / 0
-
-
2.9
-
2.9
-
2.9
-
2.9
-
5.8
-
5.8
Units
ns
ns
ns
ns
ns
ns
ns
ns
CLB Shift Register Switching Characteristics
Symbol
Description
Sequential Delays
T_REG
Clock CLK to X/Y outputs
Setup Times with Respect to Clock CLK
T_SHDICK
T_SHCECK
Clock CLK
BX/BY data inputs (DIN)
CE input (WS)
T_SRPH
T_SRPL
Minimum pulse width, High
Minimum pulse width, Low
Speed Grade
-6
-5
Min Max Min Max
Units
-
3.47
-
3.88 ns
0.8
-
0.9
-
ns
0.9
-
1.0
-
ns
-
2.9
-
2.9
ns
-
2.9
-
2.9
ns
DS001-3 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 3 of 4
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