DS001 Datasheet, PDF (46/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: Functional Description
SSTL3 Class I
A sample circuit illustrating a valid termination technique for
SSTL3_I appears in Figure 47. DC voltage specifications
appear in Table 25 for the SSTL3_I standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics.
SSTL3 Class II
A sample circuit illustrating a valid termination technique for
SSTL3_II appears in Figure 48. DC voltage specifications
appear in Table 26 for the SSTL3_II standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics.
SSTL3 Class I
V_CCO = 3.3V
25Ω
V_TT = 1.5V
50Ω
Z = 50
V_REF = 1.5V
DS001_47_061200
Figure 47: Terminated SSTL3 Class I
Table 25: SSTL3_I Voltage Specifications
Parameter
Min Typ
V_CCO
V_REF = 0.45 × V_CCO
V_TT = V_REF
V_IH ≥ V_REF + 0.2
V_IL ≤ V_REF – 0.2
V_OH ≥ V_REF + 0.6
V_OL ≤ V_REF – 0.6
I_OH at V_OH (mA)
I_OL at V_OL (mA)
3.0 3.3
1.3 1.5
1.3 1.5
1.5 1.7
–0.3⁽²⁾ 1.3
1.9
-
-
-
–8
-
8
-
Notes:
1. V_IH maximum is V_CCO + 0.3.
2. V_IL minimum does not conform to the formula.
Max
3.6
1.7
1.7
3.9⁽¹⁾
1.5
-
1.1
-
-
SSTL3 Class II
V_TT = 1.5V
V_CCO = 3.3V
50Ω
25Ω
V_TT = 1.5V
50Ω
Z = 50
V_REF = 1.5V
DS001_48_061200
Figure 48: Terminated SSTL3 Class II
Table 26: SSTL3_II Voltage Specifications
Parameter
Min Typ
V_CCO
V_REF = 0.45 × V_CCO
V_TT = V_REF
V_IH ≥ V_REF + 0.2
V_IL ≤ V_REF – 0.2
V_OH ≥ V_REF + 0.8
V_OL ≤ V_REF – 0.8
I_OH at V_OH (mA)
I_OL at V_OL (mA)
3.0 3.3
1.3 1.5
1.3 1.5
1.5 1.7
–0.3⁽²⁾ 1.3
2.1
-
-
-
–16
-
16
-
Notes:
1. V_IH maximum is V_CCO + 0.3
2. V_IL minimum does not conform to the formula
Max
3.6
1.7
1.7
3.9⁽¹⁾
1.5
-
0.9
-
-
DS001-2 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
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