DS001 Datasheet, PDF (57/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: DC and Switching Characteristics
IOB Input Delay Adjustments for Different Standards⁽¹⁾
Input delays associated with the pad are specified for LVTTL. For other standards, adjust the delays by the values shown. A
delay adjusted in this way constitutes a worst-case limit.
Speed Grade
Symbol
Description
Standard
-6
-5
Units
Data Input Delay Adjustments
T_ILVTTL Standard-specific data input delay
T_ILVCMOS2 ^adjustments
LVTTL
LVCMOS2
0
0
ns
–0.04
–0.05
ns
T_{IPCI33_3}
PCI, 33 MHz, 3.3V
–0.11
–0.13
ns
T_{IPCI33_5}
PCI, 33 MHz, 5.0V
0.26
0.30
ns
T_{IPCI66_3}
PCI, 66 MHz, 3.3V
–0.11
–0.13
ns
T_IGTL
GTL
0.20
0.24
ns
T_IGTLP
GTL+
0.11
0.13
ns
T_IHSTL
HSTL
0.03
0.04
ns
T_ISSTL2
SSTL2
–0.08
–0.09
ns
T_ISSTL3
SSTL3
–0.04
–0.05
ns
T_ICTT
CTT
0.02
0.02
ns
T_IAGP
AGP
–0.06
–0.07
ns
Notes:
1. Input timing for LVTTL is measured at 1.4V. For other I/O standards, see the table "Delay Measurement Methodology," page 60.
1
DS001-3 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
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