DS001 Datasheet, PDF (70/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: Pinout Tables
Table 36: Spartan-II Family Package Options
Package
Leads
Type
VQ100 / VQG100
TQ144 / TQG144
CS144 / CSG144
PQ208 / PQG208
FG256 / FGG256
FG456 / FGG456
100 Very Thin Quad Flat Pack (VQFP)
144 Thin Quad Flat Pack (TQFP)
144 Chip Scale Ball Grid Array (CSBGA)
208 Plastic Quad Flat Pack (PQFP)
256 Fine-pitch Ball Grid Array (FBGA)
456 Fine-pitch Ball Grid Array (FBGA)
Notes:
1. Package mass is ±10%.
Maximum
I/O
60
92
92
140
176
284
Lead Pitch
(mm)
0.5
0.5
0.8
0.5
1.0
1.0
Footprint
Area (mm)
16 x 16
22 x 22
12 x 12
30.6 x 30.6
17 x 17
23 x 23
Height
(mm)
1.20
1.60
1.20
3.70
2.00
2.60
Mass⁽¹⁾
(g)
0.6
1.4
0.3
5.3
0.9
2.2
Note: Some early versions of Spartan-II devices, including
the XC2S15 and XC2S30 ES devices and the XC2S150
with date code 0045 or earlier, included a power-down pin.
For more information, see Answer Record 10500.
VCCO Banks
Some of the I/O standards require specific V_CCO voltages.
These voltages are externally connected to device pins that
serve groups of IOBs, called banks. Eight I/O banks result
from separating each edge of the FPGA into two banks (see
Figure 3 in Module 2). Each bank has multiple V_CCO pins
which must be connected to the same voltage. In the
smaller packages, the V_CCO pins are connected between
banks, effectively reducing the number of independent
banks available (see Table 37). These interconnected
banks are shown in the Pinout Tables with V_CCO pads for
multiple banks connected to the same pin.
Table 37: Independent VCCO Banks Available
Package
VQ100
PQ208
CS144
TQ144
FG256
FG456
Independent Banks
1
4
8
Package Overview
Table 36 shows the six low-cost, space-saving production
package styles for the Spartan-II family.
Each package style is available in an environmentally
friendly lead-free (Pb-free) option. The Pb-free packages
include an extra ‘G’ in the package style name. For
example, the standard “CS144” package becomes
“CSG144” when ordered as the Pb-free option. Leaded
(non-Pb-free) packages may be available for selected
devices, with the same pin-out and without the "G" in the
ordering code; contact Xilinx sales for more information.
The mechanical dimensions of the standard and Pb-free
packages are similar, as shown in the mechanical drawings
provided in Table 38.
For additional package information, see UG112: Device
Package User Guide.
Mechanical Drawings
Detailed mechanical drawings for each package type are
available from the Xilinx web site at the specified location in
Table 38.
Material Declaration Data Sheets (MDDS) are also
available on the Xilinx web site for each package.
Table 38: Xilinx Package Documentation
Package
Drawing
MDDS
VQ100
Package Drawing PK173_VQ100
VQG100
PK130_VQG100
TQ144
Package Drawing PK169_TQ144
TQG144
PK126_TQG144
CS144
Package Drawing PK149_CS144
CSG144
PK103_CSG144
PQ208
Package Drawing PK166_PQ208
PQG208
PK123_PQG208
FG256
Package Drawing PK151_FG256
FGG256
PK105_FGG256
FG456
Package Drawing PK154_FG456
FGG456
PK109_FGG456
DS001-4 (v2.8) June 13, 2008
Product Specification
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