DS001 Datasheet, PDF (63/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: DC and Switching Characteristics
Period Tolerance: the allowed input clock period change in nanoseconds.
TCLKIN =
1
FCLKIN
TCLKIN +_ TIPTOL
Output Jitter: the difference between an ideal
reference clock edge and the actual design. Phase Offset and Maximum Phase Difference
Ideal Period
Actual Period
+/- Jitter
+ Maximum
Phase Difference
+ Phase Offset
DS001_52_090800
Figure 52: Period Tolerance and Clock Jitter
DS001-3 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 3 of 4
63