DS001 Datasheet, PDF (35/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

R
Spartan-II FPGA Family: Functional Description
CLK
ADDR
DIN
DOUT
EN
TBPWH
TBPWL
TBACK
00
TBDCK
DDDD
TBCKO
MEM (00)
TBECK
0F
CCCC
CCCC
7E
8F
BBBB
2222
MEM (7E)
RST
WE
DISABLED
TBWCK
READ
WRITE
READ
DISABLED
DS001_33_061200
Figure 33: Timing Diagram for Single-Port Block RAM Memory
CLK_A
ADDR_A
EN_A
WE_A
DI_A
DO_A
TBCCS
VIOLATION
00
7E
0F
T_BCCS
0F
7E
T_BCCS
AAAA
AAAA
9999
9999
AAAA
AAAA
0000
1111
UNKNOWN
2222
CLK_B
ADDR_B
00
00
7E
0F
0F
7E
1A
EN_B
WE_B
DI_B
1111
1111
1111
BBBB
1111
2222
FFFF
DO_B
MEM (00)
AAAA
9999
BBBB
UNKNOWN
2222
FFFF
Figure 34: Timing Diagram for a True Dual-Port Read/Write Block RAM Memory
DS001_34_061200
DS001-2 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 2 of 4
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