DS001 Datasheet, PDF (29/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: Functional Description
division factor N except for non-integer division in High
Frequency (HF) mode. For division factor 1.5 the duty cycle
in the HF mode is 33.3% High and 66.7% Low. For division
factor 2.5, the duty cycle in the HF mode is 40.0% High and
60.0% Low.
1x Clock Outputs — CLK[0|90|180|270]
The 1x clock output pin CLK0 represents a
delay-compensated version of the source clock (CLKIN)
signal. The CLKDLL primitive provides three phase-shifted
versions of the CLK0 signal while CLKDLLHF provides only
the 180 degree phase-shifted version. The relationship
between phase shift and the corresponding period shift
appears in Table 10.
The timing diagrams in Figure 26 illustrate the DLL clock
output characteristics.
Table 10: Relationship of Phase-Shifted Output Clock
to Period Shift
Phase (degrees)
Period Shift (percent)
0
0%
90
25%
180
50%
270
75%
The DLL provides duty cycle correction on all 1x clock
outputs such that all 1x clock outputs by default have a
50/50 duty cycle. The DUTY_CYCLE_CORRECTION
property (TRUE by default), controls this feature. In order to
deactivate the DLL duty cycle correction, attach the
DUTY_CYCLE_CORRECTION=FALSE property to the
DLL primitive. When duty cycle correction deactivates, the
output clock has the same duty cycle as the source clock.
The DLL clock outputs can drive an OBUF, a BUFG, or they
can route directly to destination clock pins. The DLL clock
outputs can only drive the BUFGs that reside on the same
edge (top or bottom).
Locked Output — LOCKED
In order to achieve lock, the DLL may need to sample
several thousand clock cycles. After the DLL achieves lock
the LOCKED signal activates. The "DLL Timing
Parameters" section of Module 3 provides estimates for
locking times.
In order to guarantee that the system clock is established
prior to the device "waking up," the DLL can delay the
completion of the device configuration process until after
the DLL locks. The STARTUP_WAIT property activates this
feature.
Until the LOCKED signal activates, the DLL output clocks
are not valid and can exhibit glitches, spikes, or other
spurious movement. In particular the CLK2X output will
appear as a 1x clock with a 25/75 duty cycle.
DLL Properties
Properties provide access to some of the Spartan-II family
DLL features, (for example, clock division and duty cycle
correction).
Duty Cycle Correction Property
The 1x clock outputs, CLK0, CLK90, CLK180, and CLK270,
use the duty-cycle corrected default, such that they exhibit a
50/50 duty cycle. The DUTY_CYCLE_CORRECTION
property (by default TRUE) controls this feature. To
deactivate the DLL duty-cycle correction for the 1x clock
outputs, attach the DUTY_CYCLE_CORRECTION=FALSE
property to the DLL primitive.
CLKIN
0 90 180 270 0 90 180 270
T
CLK2X
CLKDV_DIVIDE = 2
CLKDV
DUTY_CYCLE_CORRECTION = FALSE
CLK0
CLK90
CLK180
CLK270
DUTY_CYCLE_CORRECTION = TRUE
CLK0
CLK90
CLK180
CLK270
DS001_26_032300
Figure 26: DLL Output Characteristics
Clock Divide Property
The CLKDV_DIVIDE property specifies how the signal on
the CLKDV pin is frequency divided with respect to the
CLK0 pin. The values allowed for this property are 1.5, 2,
2.5, 3, 4, 5, 8, or 16; the default value is 2.
DS001-2 (v2.8) June 13, 2008
Product Specification
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