DS001 Datasheet, PDF (26/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

R
Spartan-II FPGA Family: Functional Description
CCLK
CS
T_SMCSCC
WRITE
T_SMCCW
T_SMDCC
DATA[7:0]
BUSY
T_SMCKBY
T_SMCCD
T_SMCCCS
T_SMWCC
Symbol
T_SMDCC
T_SMCCD
T_SMCSCC
T_SMCCCS
T_SMCCW
T_SMWCC
T_SMCKBY
F_CC
F_CCNH
No Write
CCLK
Write
No Write
Write
Description
D0-D7 setup/hold
5
D0-D7 hold
0
CS setup
7
CS hold
0
WRITE setup
7
WRITE hold
0
BUSY propagation delay
12
Maximum frequency
66
Maximum frequency with no handshake 50
DS001_20_061200
Units
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, max
MHz, max
MHz, max
Figure 20: Slave Parallel Write Timing
CCLK
CS
WRITE
DATA[7:0]
BUSY
DS001-2 (v2.8) June 13, 2008
Product Specification
Abort
Figure 21: Slave Parallel Write Abort Waveforms
www.xilinx.com
DS001_21_032300
Module 2 of 4
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