DS001 Datasheet, PDF (67/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: DC and Switching Characteristics
Block RAM Switching Characteristics
Symbol
Description
Sequential Delays
T_BCKO
Clock CLK to DOUT output
Setup/Hold Times with Respect to Clock CLK⁽¹⁾
T_BACK / T_BCKA
T_BDCK/ T_BCKD
T_BECK/ T_BCKE
T_BRCK/ T_BCKR
T_BWCK/ T_BCKW
Clock CLK
ADDR inputs
DIN inputs
EN inputs
RST input
WEN input
T_BPWH
Minimum pulse width, High
T_BPWL
Minimum pulse width, Low
T_BCCS
CLKA -> CLKB setup time for different ports
Notes:
1. A zero hold time listing indicates no hold time or a negative hold time.
Speed Grade
-6
-5
Min
Max
Min
Max
-
3.4
-
4.0
1.4 / 0
-
1.4 / 0
-
1.4 / 0
-
1.4 / 0
-
2.9 / 0
-
3.2 / 0
-
2.7 / 0
-
2.9 / 0
-
2.6 / 0
-
2.8 / 0
-
-
1.9
-
1.9
-
1.9
-
1.9
-
3.0
-
4.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
TBUF Switching Characteristics
Symbol
Description
Combinatorial Delays
T_IO
T_OFF
T_ON
IN input to OUT output
TRI input to OUT output high impedance
TRI input to valid data on OUT output
Speed Grade
-6
-5
Max
Max
0
0
0.1
0.2
0.1
0.2
Units
ns
ns
ns
JTAG Test Access Port Switching Characteristics
Symbol
Description
Setup and Hold Times with Respect to TCK
T_{TAPTCK /} T_TCKTAP TMS and TDI setup and hold times
Sequential Delays
T_TCKTDO
FTCK
Output delay from clock TCK to output TDO
Maximum TCK clock frequency
Speed Grade
-6
-5
Min
Max
Min
Max
4.0 / 2.0
-
4.0 / 2.0
-
-
11.0
-
11.0
-
33
-
33
Units
ns
ns
MHz
DS001-3 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 3 of 4
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