DS001 Datasheet, PDF (9/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: Functional Description
drivers are disabled. Maintaining a valid logic level in this
way helps eliminate bus chatter.
Because the weak-keeper circuit uses the IOB input buffer
to monitor the input level, an appropriate V_REF voltage must
be provided if the signaling standard requires one. The
provision of this voltage must comply with the I/O banking
rules.
I/O Banking
Some of the I/O standards described above require V_CCO
and/or V_REF voltages. These voltages are externally
connected to device pins that serve groups of IOBs, called
banks. Consequently, restrictions exist about which I/O
standards can be combined within a given bank.
Eight I/O banks result from separating each edge of the
FPGA into two banks (see Figure 3). Each bank has
multiple V_CCO pins which must be connected to the same
voltage. Voltage is determined by the output standards in
use.
Bank 0
Bank 1
GCLK3 GCLK2
automatically configured as inputs for the V_REF voltage.
About one in six of the I/O pins in the bank assume this role.
V_REF pins within a bank are interconnected internally and
consequently only one V_REF voltage can be used within
each bank. All V_REF pins in the bank, however, must be
connected to the external voltage source for correct
operation.
In a bank, inputs requiring V_REF can be mixed with those
that do not but only one V_REF voltage may be used within a
bank. Input buffers that use V_REF are not 5V tolerant.
LVTTL, LVCMOS2, and PCI are 5V tolerant. The V_CCO and
V_REF pins for each bank appear in the device pinout tables.
Within a given package, the number of V_REF and V_CCO pins
can vary depending on the size of device. In larger devices,
more I/O pins convert to V_REF pins. Since these are always
a superset of the V_REF pins used for smaller devices, it is
possible to design a PCB that permits migration to a larger
device. All V_REF pins for the largest device anticipated must
be connected to the V_REF voltage, and not used for I/O.
Independent Banks Available
Package
VQ100
PQ208
CS144
TQ144
FG256
FG456
Independent Banks
1
4
8
Spartan-II
Device
GCLK1 GCLK0
Bank 5
Bank 4
DS001_03_060100
Figure 3: Spartan-II I/O Banks
Within a bank, output standards may be mixed only if they
use the same V_CCO. Compatible standards are shown in
Table 4. GTL and GTL+ appear under all voltages because
their open-drain outputs do not depend on V_CCO.
Table 4: Compatible Output Standards
V_CCO
Compatible Standards
3.3V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP,
GTL, GTL+
2.5V SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+
1.5V HSTL I, HSTL III, HSTL IV, GTL, GTL+
Some input standards require a user-supplied threshold
voltage, V_REF. In this case, certain user-I/O pins are
Configurable Logic Block
The basic building block of the Spartan-II FPGA CLB is the
logic cell (LC). An LC includes a 4-input function generator,
carry logic, and storage element. Output from the function
generator in each LC drives the CLB output and the D input
of the flip-flop. Each Spartan-II FPGA CLB contains four
LCs, organized in two similar slices; a single slice is shown
in Figure 4.
In addition to the four basic LCs, the Spartan-II FPGA CLB
contains logic that combines function generators to provide
functions of five or six inputs.
Look-Up Tables
Spartan-II FPGA function generators are implemented as
4-input look-up tables (LUTs). In addition to operating as a
function generator, each LUT can provide a 16 x 1-bit
synchronous RAM. Furthermore, the two LUTs within a
slice can be combined to create a 16 x 2-bit or 32 x 1-bit
synchronous RAM, or a 16 x 1-bit dual-port synchronous
RAM.
The Spartan-II FPGA LUT can also provide a 16-bit shift
register that is ideal for capturing high-speed or burst-mode
data. This mode can also be used to store data in
applications such as Digital Signal Processing.
DS001-2 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
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