DS001 Datasheet, PDF (53/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: DC and Switching Characteristics
Power-On Requirements
Spartan-II FPGAs require that a minimum supply current
I_CCPO be provided to the V_CCINT lines for a successful
power-on. If more current is available, the FPGA can
consume more than I_CCPO minimum, though this cannot
adversely affect reliability.
A maximum limit for I_CCPO is not specified. Therefore the
use of foldback/crowbar supplies and fuses deserves
special attention. In these cases, limit the I_CCPO current to a
level below the trip point for over-current protection in order
to avoid inadvertently shutting down the supply.
Conditions
New
Requirements⁽¹⁾
For Devices with
Date Code 0321
or Later
Old
Requirements⁽¹⁾
For Devices with
Date Code
before 0321
Symbol
Description
Device
Junction
Temperature
Temperature⁽²⁾
Grade
Min
Max
Min
Max Units
I
(3)
CCPO
Total V_CCINT supply
–40°C ≤ T_J < –20°C Industrial
1.50
-
2.00
-
A
current required
during power-on
–20°C ≤ T_J < 0°C
Industrial
1.00
-
2.00
-
0°C ≤ T_J ≤ 85°C Commercial 0.25
-
0.50
-
A
A
85°C < T_J ≤ 100°C Industrial
0.50
-
0.50
-
A
T_CCPO(4,5) V_CCINT ramp time
–40°C≤ T_J≤ 100°C
All
-
50
-
50
ms
Notes:
1. The date code is printed on the top of the device’s package. See the "Device Part Marking" section in Module 1.
2. The expected T_J range for the design determines the I_CCPO minimum requirement. Use the applicable ranges in the junction
temperature column to find the associated current values in the appropriate new or old requirements column according to the date
code. Then choose the highest of these current values to serve as the minimum I_CCPO requirement that must be met. For example,
if the junction temperature for a given design is -25°C ≤ T_J ≤ 75°C, then the new minimum I_CCPO requirement is 1.5A.
If 5°C ≤ T_J ≤ 90°C, then the new minimum I_CCPO requirement is 0.5A.
3. The I_CCPO requirement applies for a brief time (commonly only a few milliseconds) when V_CCINT ramps from 0 to 2.5V.
4. The ramp time is measured from GND to V_CCINT max on a fully loaded board.
5. During power-on, the V_CCINT ramp must increase steadily in voltage with no dips.
6. For more information on designing to meet the power-on specifications, refer to the application note XAPP450 "Power-On Current
Requirements for the Spartan-II and Spartan-IIE Families"
DC Input and Output Levels
Values for V_IL and V_IH are recommended input voltages.
Values for V_OL and V_OH are guaranteed output voltages
over the recommended operating conditions. Only selected
standards are tested. These are chosen to ensure that all
standards meet their specifications. The selected standards
are tested at minimum V_CCO with the respective I_OL and I_OH
currents shown. Other standards are sample tested.
Input/Output
Standard
LVTTL⁽¹⁾
LVCMOS2
PCI, 3.3V
PCI, 5.0V
GTL
GTL+
HSTL I
HSTL III
HSTL IV
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
V, Min
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
V_IL
V, Max
0.8
0.7
44% V_CCINT
0.8
V_REF – 0.05
V_REF – 0.1
V_REF – 0.1
V_REF – 0.1
V_REF – 0.1
V_REF – 0.2
V_REF – 0.2
V_REF – 0.2
V_REF – 0.2
V_IH
V, Min
V, Max
2.0
5.5
1.7
5.5
60% V_CCINT
2.0
V_CCO + 0.5
5.5
V_REF + 0.05
3.6
V_REF + 0.1
3.6
V_REF + 0.1
3.6
V_REF + 0.1
3.6
V_REF + 0.1
3.6
V_REF + 0.2
3.6
V_REF + 0.2
3.6
V_REF + 0.2
3.6
V_REF + 0.2
3.6
V_OL
V, Max
0.4
0.4
10% V_CCO
0.55
0.4
0.6
0.4
0.4
0.4
V_REF – 0.6
V_REF – 0.8
V_REF – 0.6
V_REF – 0.8
V_OH
V, Min
2.4
1.9
90% V_CCO
2.4
N/A
N/A
V_CCO – 0.4
V_CCO – 0.4
V_CCO – 0.4
V_REF + 0.6
V_REF + 0.8
V_REF + 0.6
V_REF + 0.8
I_OL
mA
24
12
Note (2)
Note (2)
40
36
8
24
48
8
16
7.6
15.2
I_OH
mA
–24
–12
Note (2)
Note (2)
N/A
N/A
–8
–8
–8
–8
–16
–7.6
–15.2
DS001-3 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
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