DS001 Datasheet, PDF (17/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: Functional Description
Configuration
Configuration is the process by which the bitstream of a
design, as generated by the Xilinx software, is loaded into
the internal configuration memory of the FPGA. Spartan-II
devices support both serial configuration, using the
master/slave serial and JTAG modes, as well as byte-wide
configuration employing the Slave Parallel mode.
Table 8: Spartan-II Configuration File Size
Device
Configuration File Size (Bits)
XC2S15
197,696
XC2S30
336,768
XC2S50
559,200
Configuration File
XC2S100
781,216
Spartan-II devices are configured by sequentially loading
frames of data that have been concatenated into a
configuration file. Table 8 shows how much nonvolatile
storage space is needed for Spartan-II devices.
It is important to note that, while a PROM is commonly used
to store configuration data before loading them into the
FPGA, it is by no means required. Any of a number of
different kinds of under populated nonvolatile storage
already available either on or off the board (i.e., hard drives,
FLASH cards, etc.) can be used. For more information on
configuration without a PROM, refer to XAPP098, The
Low-Cost, Efficient Serial Configuration of Spartan FPGAs.
XC2S150
XC2S200
1,040,096
1,335,840
Modes
Spartan-II devices support the following four configuration
modes:
• Slave Serial mode
• Master Serial mode
• Slave Parallel mode
• Boundary-scan mode
The Configuration mode pins (M2, M1, M0) select among
these configuration modes with the option in each case of
having the IOB pins either pulled up or left floating prior to
the end of configuration. The selection codes are listed in
Table 9.
Configuration through the boundary-scan port is always
available, independent of the mode selection. Selecting the
boundary-scan mode simply turns off the other modes. The
three mode pins have internal pull-up resistors, and default
to a logic High if left unconnected.
Table 9: Configuration Modes
Configuration Mode
Master Serial mode
Preconfiguration
Pull-ups
M0 M1 M2
No
000
CCLK
Direction
Out
Data Width
1
Serial D_OUT
Yes
Yes
001
Slave Parallel mode
Yes
010
In
8
No
No
011
Boundary-Scan mode
Yes
100
N/A
1
No
No
101
Slave Serial mode
Yes
110
In
1
Yes
No
111
Notes:
1. During power-on and throughout configuration, the I/O drivers will be in a high-impedance state. After configuration, all unused I/Os
(those not assigned signals) will remain in a high-impedance state. Pins used as outputs may pulse High at the end of configuration
(see Answer 10504).
2. If the Mode pins are set for preconfiguration pull-ups, those resistors go into effect once the rising edge of INIT samples the Mode
pins. They will stay in effect until GTS is released during startup, after which the UnusedPin bitstream generator option will determine
whether the unused I/Os have a pull-up, pull-down, or no resistor.
DS001-2 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
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