DS001 Datasheet, PDF (39/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: Functional Description
the LOC property is described below. Table 16 summarizes
the input standards compatibility requirements.
An optional delay element is associated with each IBUF.
When the IBUF drives a flip-flop within the IOB, the delay
element by default activates to ensure a zero hold-time
requirement. The NODELAY=TRUE property overrides this
default.
When the IBUF does not drive a flip-flop within the IOB, the
delay element de-activates by default to provide higher
performance. To delay the input signal, activate the delay
element with the DELAY=TRUE property.
Bank 0
Bank 1
GCLK3 GCLK2
Spartan-II
Device
GCLK1 GCLK0
Bank 5
Bank 4
Figure 36: I/O Banks
DS001_03_060100
Table 16: Xilinx Input Standards Compatibility
Requirements
Rule 1 All differential amplifier input signals within a
bank are required to be of the same standard.
Rule 2 There are no placement restrictions for inputs
with standards that require a single-ended input
buffer.
IBUFG
Signals used as high fanout clock inputs to the
Spartan-II device should drive a global clock input buffer
(IBUFG) via an external input port in order to take
advantage of one of the four dedicated global clock
distribution networks. The output of the IBUFG primitive can
only drive a CLKDLL, CLKDLLHF, or a BUFG primitive. The
generic IBUFG primitive appears in Figure 37.
IBUFG
I
O
DS001_37_061200
Figure 37: Global Clock Input Buffer (IBUFG) Primitive
With no extension or property specified for the generic
IBUFG primitive, the assumed standard is LVTTL.
The voltage reference signal is "banked" within the
Spartan-II device on a half-edge basis such that for all
packages there are eight independent V_REF banks
internally. See Figure 36 for a representation of the I/O
banks. Within each bank approximately one of every six I/O
pins is automatically configured as a V_REF input.
IBUFG placement restrictions require any differential
amplifier input signals within a bank be of the same
standard. The LOC property can specify a location for the
IBUFG.
As an added convenience, the BUFGP can be used to
instantiate a high fanout clock input. The BUFGP primitive
represents a combination of the LVTTL IBUFG and BUFG
primitives, such that the output of the BUFGP can connect
directly to the clock pins throughout the design.
The Spartan-II FPGA BUFGP primitive can only be placed
in a global clock pad location. The LOC property can specify
a location for the BUFGP.
OBUF
An OBUF must drive outputs through an external output
port. The generic output buffer (OBUF) primitive appears in
Figure 38.
OBUF
I
O
DS001_38_061200
Figure 38: Output Buffer (OBUF) Primitive
With no extension or property specified for the generic
OBUF primitive, the assumed standard is slew rate limited
LVTTL with 12 mA drive strength.
The LVTTL OBUF additionally can support one of two slew
rate modes to minimize bus transients. By default, the slew
rate for each output buffer is reduced to minimize power bus
transients when switching non-critical signals.
DS001-2 (v2.8) June 13, 2008
Product Specification
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