DS001 Datasheet, PDF (24/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

R
DATA[7:0]
CCLK
WRITE
BUSY
Spartan-II FPGA Family: Functional Description
M1 M2
M0
M1 M2
M0
CS(0)
Spartan-II
FPGA
D0:D7
CCLK
WRITE
BUSY
CS
CS(1)
Spartan-II
FPGA
D0:D7
CCLK
WRITE
BUSY
CS
DONE
INIT
PROGRAM
330Ω
PROGRAM
DONE
INIT
GND
PROGRAM
DONE
INIT
GND
Figure 18: Slave Parallel Configuration Circuit Diagram
DS001_18_060608
Multiple Spartan-II FPGAs can be configured using the
Slave Parallel mode, and be made to start-up
simultaneously. To configure multiple devices in this way,
wire the individual CCLK, Data, WRITE, and BUSY pins of
all the devices in parallel. The individual devices are loaded
separately by asserting the CS pin of each device in turn
and writing the appropriate data. Sync-to-DONE start-up
timing is used to ensure that the start-up sequence does not
begin until all the FPGAs have been loaded. See "Start-up,"
page 19.
Write
When using the Slave Parallel Mode, write operations send
packets of byte-wide configuration data into the FPGA.
Figure 19, page 25 shows a flowchart of the write sequence
used to load data into the Spartan-II FPGA. This is an
expansion of the "Load Configuration Data Frames" block in
Figure 11, page 18. The timing for write operations is shown
in Figure 20, page 26.
For the present example, the user holds WRITE and CS
Low throughout the sequence of write operations. Note that
when CS is asserted on successive CCLKs, WRITE must
remain either asserted or de-asserted. Otherwise an abort
will be initiated, as in the next section.
1. Drive data onto D0-D7. Note that to avoid contention,
the data source should not be enabled while CS is Low
and WRITE is High. Similarly, while WRITE is High, no
more than one device’s CS should be asserted.
2. On the rising edge of CCLK: If BUSY is Low, the data is
accepted on this clock. If BUSY is High (from a previous
write), the data is not accepted. Acceptance will instead
occur on the first clock after BUSY goes Low, and the
data must be held until this happens.
3. Repeat steps 1 and 2 until all the data has been sent.
4. De-assert CS and WRITE.
DS001-2 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
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