DS001 Datasheet, PDF (61/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: DC and Switching Characteristics
Clock Distribution Guidelines⁽¹⁾
Speed Grade
-6
-5
Symbol
Description
Max
Max
Units
GCLK Clock Skew
T_GSKEWIOB
Global clock skew between IOB flip-flops
0.13
0.14
ns
Notes:
1. These clock distribution delays are provided for guidance only. They reflect the delays encountered in a typical design under
worst-case conditions. Precise values for a particular design are provided by the timing analyzer.
Clock Distribution Switching Characteristics
T_GPIO is specified for LVTTL levels. For other standards, adjust T_GPIO with the values shown in "I/O Standard Global Clock
Input Adjustments".
Speed Grade
-6
-5
Symbol
Description
Max
Max
Units
GCLK IOB and Buffer
T_GPIO
T_GIO
Global clock pad to output
Global clock buffer I input to O output
0.7
0.8
ns
0.7
0.8
ns
I/O Standard Global Clock Input Adjustments
Delays associated with a global clock input pad are specified for LVTTL levels. For other standards, adjust the delays by the
values shown. A delay adjusted in this way constitutes a worst-case limit.
Speed Grade
Symbol
Description
Standard
-6
-5
Units
Data Input Delay Adjustments
T_GPLVTTL
T_GPLVCMOS2
Standard-specific global clock
input delay adjustments
LVTTL
LVCMOS2
0
0
ns
–0.04
–0.05
ns
T_{GPPCI33_3}
PCI, 33 MHz, 3.3V
–0.11
–0.13
ns
T_{GPPCI33_5}
PCI, 33 MHz, 5.0V
0.26
0.30
ns
T_{GPPCI66_3}
PCI, 66 MHz, 3.3V
–0.11
–0.13
ns
T_GPGTL
GTL
0.80
0.84
ns
T_GPGTLP
GTL+
0.71
0.73
ns
T_GPHSTL
HSTL
0.63
0.64
ns
T_GPSSTL2
SSTL2
0.52
0.51
ns
T_GPSSTL3
SSTL3
0.56
0.55
ns
T_GPCTT
CTT
0.62
0.62
ns
T_GPAGP
AGP
0.54
0.53
ns
Notes:
1. Input timing for GPLVTTL is measured at 1.4V. For other I/O standards, see the table "Delay Measurement Methodology," page 60.
1
DS001-3 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
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