DS001 Datasheet, PDF (62/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: DC and Switching Characteristics
DLL Timing Parameters
All devices are 100 percent functionally tested. Because of
the difficulty in directly measuring many internal timing
parameters, those parameters are derived from benchmark
timing patterns. The following guidelines reflect worst-case
values across the recommended operating conditions.
Symbol
F_CLKINHF
F_CLKINLF
T_DLLPWHF
T_DLLPWLF
Description
Input clock frequency (CLKDLLHF)
Input clock frequency (CLKDLL)
Input clock pulse width (CLKDLLHF)
Input clock pulse width (CLKDLL)
Speed Grade
-6
-5
Min
Max
Min
Max
60
200
60
180
25
100
25
90
2.0
-
2.4
-
2.5
-
3.0
-
Units
MHz
MHz
ns
ns
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications were
determined through statistical measurement at the package
pins using a clock mirror configuration and matched drivers.
Figure 52, page 63, provides definitions for various
parameters in the table below.
CLKDLLHF CLKDLL
Symbol
T_IPTOL
T_IJITCC
T_LOCK
Description
Input clock period tolerance
Input clock jitter tolerance (cycle-to-cycle)
Time required for DLL to acquire lock
F_CLKIN
> 60 MHz
50-60 MHz
Min Max Min Max Units
-
1.0
-
1.0
ns
- ±150 - ±300 ps
-
20
-
20
μs
-
-
-
25
μs
40-50 MHz
-
-
-
50
μs
30-40 MHz
-
-
-
90
μs
25-30 MHz
-
-
-
120
μs
T_OJITCC Output jitter (cycle-to-cycle) for any DLL clock output⁽¹⁾
-
±60
-
±60
ps
T_PHIO Phase offset between CLKIN and CLKO⁽²⁾
- ±100 - ±100 ps
T_PHOO Phase offset between clock outputs on the DLL⁽³⁾
- ±140 - ±140 ps
T_PHIOM Maximum phase difference between CLKIN and CLKO⁽⁴⁾
- ±160 - ±160 ps
T_PHOOM Maximum phase difference between clock outputs on the DLL⁽⁵⁾
-
± 200
-
± 200
ps
Notes:
1. Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter.
2. Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding output jitter and input clock jitter.
3. Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding Output Jitter and input clock jitter.
4. Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO,
or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
5. Maximum Phase Difference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges due to DLL alone (excluding input clock jitter).
DS001-3 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
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