DS001 Datasheet, PDF (2/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

6
R
DS001-1 (v2.8) June 13, 2008
0
Introduction
The Spartan^®-II Field-Programmable Gate Array family
gives users high performance, abundant logic resources,
and a rich feature set, all at an exceptionally low price. The
six-member family offers densities ranging from 15,000 to
200,000 system gates, as shown in Table 1. System
performance is supported up to 200 MHz. Features include
block RAM (to 56K bits), distributed RAM (to 75,264 bits),
16 selectable I/O standards, and four DLLs. Fast,
predictable interconnect means that successive design
iterations continue to meet timing requirements.
The Spartan-II family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial
cost, lengthy development cycles, and inherent risk of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary (impossible with ASICs).
Features
• Second generation ASIC replacement technology
- Densities as high as 5,292 logic cells with up to
200,000 system gates
- Streamlined features based on Virtex^® FPGA
architecture
- Unlimited reprogrammability
- Very low cost
- Cost-effective 0.18 micron process
Spartan-II FPGA Family:
Introduction and Ordering
Information
Product Specification
• System level features
- SelectRAM™ hierarchical memory:
· 16 bits/LUT distributed RAM
· Configurable 4K bit block RAM
· Fast interfaces to external RAM
- Fully PCI compliant
- Low-power segmented routing architecture
- Full readback ability for verification/observability
- Dedicated carry logic for high-speed arithmetic
- Efficient multiplier support
- Cascade chain for wide-input functions
- Abundant registers/latches with enable, set, reset
- Four dedicated DLLs for advanced clock control
- Four primary low-skew global clock distribution
nets
- IEEE 1149.1 compatible boundary scan logic
• Versatile I/O and packaging
- Pb-free package options
- Low-cost packages available in all densities
- Family footprint compatibility in common packages
- 16 high-performance interface standards
- Hot swap Compact PCI friendly
- Zero hold time simplifies system timing
• Core logic powered at 2.5V and I/Os powered at 1.5V,
2.5V, or 3.3V
• Fully supported by powerful Xilinx^® ISE^® development
system
- Fully automatic mapping, placement, and routing
Table 1: Spartan-II FPGA Family Members
Device
Logic
Cells
System Gates
(Logic and RAM)
CLB
Array
(R x C)
Total
CLBs
Maximum
Available
User I/O⁽¹⁾
Total
Distributed RAM
Bits
XC2S15
432
15,000
8 x 12
96
86
6,144
XC2S30
972
30,000
12 x 18 216
92
13,824
XC2S50
1,728
50,000
16 x 24 384
176
24,576
XC2S100 2,700
100,000
20 x 30 600
176
38,400
XC2S150 3,888
150,000
24 x 36 864
260
55,296
XC2S200 5,292
200,000
28 x 42 1,176
284
75,264
Notes:
1. All user I/O counts do not include the four global clock/user input pins. See details in Table 2, page 4.
Total
Block RAM
Bits
16K
24K
32K
40K
48K
56K
© 2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS001-1 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 1 of 4
2