DS001 Datasheet, PDF (43/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: Functional Description
ground metallization. The IC internal ground level deviates
from the external system ground level for a short duration (a
few nanoseconds) after multiple outputs change state
simultaneously.
Ground bounce affects stable Low outputs and all inputs
because they interpret the incoming signal by comparing it
to the internal ground. If the ground bounce amplitude
exceeds the actual instantaneous noise margin, then a
non-changing input can be interpreted as a short pulse with
a polarity opposite to the ground bounce.
Table 18 provides the guidelines for the maximum number
of simultaneously switching outputs allowed per output
power/ground pair to avoid the effects of ground bounce.
Refer to Table 19 for the number of effective output
power/ground pairs for each Spartan-II device and package
combination.
Table 18: Maximum Number of Simultaneously
Switching Outputs per Power/Ground Pair
Package
Standard
PQ,
CS, FG TQ, VQ
LVTTL Slow Slew Rate, 2 mA drive
68
36
LVTTL Slow Slew Rate, 4 mA drive
41
20
LVTTL Slow Slew Rate, 6 mA drive
29
15
LVTTL Slow Slew Rate, 8 mA drive
22
12
LVTTL Slow Slew Rate, 12 mA drive 17
9
LVTTL Slow Slew Rate, 16 mA drive 14
7
LVTTL Slow Slew Rate, 24 mA drive 9
5
LVTTL Fast Slew Rate, 2 mA drive
40
21
LVTTL Fast Slew Rate, 4 mA drive
24
12
LVTTL Fast Slew Rate, 6 mA drive
17
9
LVTTL Fast Slew Rate, 8 mA drive
13
7
LVTTL Fast Slew Rate, 12 mA drive 10
5
LVTTL Fast Slew Rate, 16 mA drive
8
4
LVTTL Fast Slew Rate, 24 mA drive
5
3
LVCMOS2
10
5
PCI
8
4
GTL
4
4
GTL+
4
4
HSTL Class I
18
9
HSTL Class III
9
5
HSTL Class IV
5
3
SSTL2 Class I
15
8
Table 18: Maximum Number of Simultaneously
Switching Outputs per Power/Ground Pair
Package
Standard
PQ,
CS, FG TQ, VQ
SSTL2 Class II
10
5
SSTL3 Class I
11
6
SSTL3 Class II
7
4
CTT
14
7
AGP
9
5
Notes:
1. This analysis assumes a 35 pF load for each output.
Table 19: Effective Output Power/Ground Pairs for
Spartan-II Devices
Spartan-II Devices
XC2S XC2S XC2S XC2S XC2S XC2S
Pkg.
15
30
50
100
150
200
VQ100 8
8
-
-
-
-
CS144 12 12
-
-
-
-
TQ144 12 12 12 12
-
-
PQ208 -
16 16 16
16
16
FG256 -
-
16 16
16
16
FG456 -
-
-
48
48
48
Termination Examples
Creating a design with the Versatile I/O features requires
the instantiation of the desired library primitive within the
design code. At the board level, designers need to know the
termination techniques required for each I/O standard.
This section describes some common application examples
illustrating the termination techniques recommended by
each of the standards supported by the Versatile I/O
features. For a full range of accepted values for the DC
voltage specifications for each standard, refer to the table
associated with each figure.
The resistors used in each termination technique example
and the transmission lines depicted represent board level
components and are not meant to represent components
on the device.
DS001-2 (v2.8) June 13, 2008
Product Specification
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