DS001 Datasheet, PDF (58/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: DC and Switching Characteristics
IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in "IOB Output Delay Adjustments for Different Standards," page 59.
Symbol
Description
Propagation Delays
T_IOOP
O input to pad
T_IOOLP
O input to pad via transparent latch
3-state Delays
T_IOTHZ
T input to pad high-impedance ⁽¹⁾
T_IOTON
T_IOTLPHZ
T input to valid data on pad
T input to pad high impedance via transparent latch⁽¹⁾
T_IOTLPON
T_GTS
T input to valid data on pad via transparent latch
GTS to pad high impedance⁽¹⁾
Sequential Delays
T_IOCKP
Clock CLK to pad
T_IOCKHZ
Clock CLK to pad high impedance (synchronous)⁽¹⁾
T_IOCKON
Clock CLK to valid data on pad (synchronous)
Setup/Hold Times with Respect to Clock CLK ⁽²⁾
T_IOOCK / T_IOCKO
T_IOOCECK /
T_IOCKOCE
T_IOSRCKO /
T_IOCKOSR
T_IOTCK / T_IOCKT
T_IOTCECK /
T_IOCKTCE
T_IOSRCKT /
T_IOCKTSR
Set/Reset Delays
O input
OCE input
SR input (OFF)
3-state setup times, T input
3-state setup times, TCE input
3-state setup times, SR input (TFF)
T_IOSRP
T_IOSRHZ
SR input to pad (asynchronous)
SR input to pad high impedance (asynchronous)⁽¹⁾
T_IOSRON
SR input to valid data on pad (asynchronous)
T_IOGSRQ
GSR to pad
Notes:
1. Three-state turn-off delays should not be adjusted.
2. A zero hold time listing indicates no hold time or a negative hold time.
Speed Grade
-6
-5
Min Max Min Max
-
2.9
-
3.4
-
3.4
-
4.0
-
2.0
-
2.3
-
3.0
-
3.6
-
2.5
-
2.9
-
3.5
-
4.2
-
5.0
-
5.9
-
2.9
-
3.4
-
2.3
-
2.7
-
3.3
-
4.0
1.1 / 0
-
1.3 / 0
-
0.9 / 0.01 - 0.9 / 0.01 -
1.2 / 0
-
1.3 / 0 -
0.8 / 0
-
0.9 / 0 -
1.0 / 0
-
1.0 / 0 -
1.1 / 0
-
1.2 / 0 -
-
3.7
-
4.4
-
3.1
-
3.7
-
4.1
-
4.9
-
9.9
-
11.7
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS001-3 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
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