DS001 Datasheet, PDF (76/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: Pinout Tables
XC2S30 Device Pinouts (Continued)
XC2S30 Pad Name
Bndry
Function Bank VQ100 TQ144 CS144 PQ208 Scan
V_CCINT
I/O
- P85 P24 A9 P171 -
1
-
P23 D8 P172 24
I/O
I/O
I/O
I/O
GND
1
-
P22 C8 P173 27
1
-
-
- P174 30
1
-
-
- P175 33
1
-
-
- P176 36
-
-
-
- P177 -
I/O, V_REF
I/O
I/O
I/O
1 P86 P21 B8 P178 39
1
-
-
- P179 42
1
-
P20 A8 P180 45
1 P87 P19 B7 P181 48
I, GCK2
GND
V_CCO
V_CCO
I, GCK3
1 P88 P18 A7 P182 54
- P89 P17 C7 P183 -
1 P90 P16 D7 P184 -
0 P90 P16 D7 P184 -
0 P91 P15 A6 P185 55
V_CCINT
I/O
I/O
I/O, V_REF
GND
I/O
I/O
I/O
- P92 P14 B6 P186 -
0
-
P13 C6 P187 62
0
-
-
- P188 65
0 P93 P12 D6 P189 68
-
-
-
- P190 -
0
-
-
- P191 71
0
-
-
- P192 74
0
-
-
- P193 77
I/O
I/O
V_CCINT
V_CCO
GND
0
-
P11 A5 P194 80
0
-
P10 B5 P195 83
-
P94 P9
C5 P196
-
0
-
-
- P197 -
-
-
P8
D5 P198
-
I/O
0 P95 P7
A4 P199 86
I/O
0 P96 P6
B4 P200 89
I/O
0
-
-
- P201 92
XC2S30 Device Pinouts (Continued)
XC2S30 Pad Name
Bndry
Function Bank VQ100 TQ144 CS144 PQ208 Scan
I/O, V_REF
I/O
0 P97 P5
0
-
-
C4 P203 95
- P204 98
I/O
I/O
TCK
V_CCO
V_CCO
04/18/01
0
-
P4
A3 P205 101
0 P98 P3
B3 P206 104
-
P99 P2
C3 P207
-
0 P100 P1
A2 P208 -
7 P100 P144 B2 P208 -
Notes:
1. IRDY and TRDY can only be accessed when using Xilinx
PCI cores.
2. See "VCCO Banks" for details on V_CCO banking.
Additional XC2S30 Package Pins
VQ100
Not Connected Pins
P28
P29
-
-
-
-
11/02/00
TQ144
Not Connected Pins
P104 P105
-
-
-
-
11/02/00
CS144
Not Connected Pins
M3
N3
-
-
-
-
11/02/00
PQ208
P7
P60
P165
11/02/00
P13
P97
P202
Not Connected Pins
P38
P44
P112 P118
-
-
P55
P143
-
P56
P149
-
Notes:
1. For the PQ208 package, P13, P38, P118, and P143, which
are Not Connected Pins on the XC2S30, are assigned to
V_CCINT on larger devices.
DS001-4 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 4 of 4
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