DS001 Datasheet, PDF (64/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: DC and Switching Characteristics
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise
values are provided by the timing analyzer.
Symbol
Description
Combinatorial Delays
T_ILO
T_IF5
T_IF5X
T_IF6Y
T_F5INY
T_IFNCTL
4-input function: F/G inputs to X/Y outputs
5-input function: F/G inputs to F5 output
5-input function: F/G inputs to X output
6-input function: F/G inputs to Y output via F6 MUX
6-input function: F5IN input to Y output
Incremental delay routing through transparent latch
to XQ/YQ outputs
T_BYYB
BY input to YB output
Sequential Delays
T_CKO
FF clock CLK to XQ/YQ outputs
T_CKLO
Latch clock CLK to XQ/YQ outputs
Setup/Hold Times with Respect to Clock CLK⁽¹⁾
T_ICK / T_CKI
T_IF5CK / T_CKIF5
T_F5INCK / T_CKF5IN
T_IF6CK / T_CKIF6
T_DICK / T_CKDI
T_CECK / T_CKCE
T_RCK / T_CKR
Clock CLK
4-input function: F/G inputs
5-input function: F/G inputs
6-input function: F5IN input
6-input function: F/G inputs via F6 MUX
BX/BY inputs
CE input
SR/BY inputs (synchronous)
T_CH
T_CL
Set/Reset
Minimum pulse width, High
Minimum pulse width, Low
T_RPW
T_RQ
Minimum pulse width, SR/BY inputs
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
T_IOGSRQ
Delay from GSR to XQ/YQ outputs
F_TOG
Toggle frequency (for export control)
Notes:
1. A zero hold time listing indicates no hold time or a negative hold time.
Speed Grade
-6
-5
Min
Max
Min
Max
-
0.6
-
0.7
-
0.7
-
0.9
-
0.9
-
1.1
-
1.0
-
1.1
-
0.4
-
0.4
-
0.7
-
0.9
-
0.6
-
0.7
-
1.1
-
1.3
-
1.2
-
1.5
1.3 / 0
-
1.4 / 0
-
1.6 / 0
-
1.8 / 0
-
1.0 / 0
-
1.1 / 0
-
1.6 / 0
-
1.8 / 0
-
0.8 / 0
-
0.8 / 0
-
0.9 / 0
-
0.9 / 0
-
0.8 / 0
-
0.8 / 0
-
-
1.9
-
1.9
-
1.9
-
1.9
3.1
-
3.1
-
-
1.1
-
1.3
-
9.9
-
11.7
-
263
-
263
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
DS001-3 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 3 of 4
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